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BU2050F-E2 bảng dữ liệu(PDF) 6 Page - Rohm |
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6 / 15 page 6/11 BU2050F TSZ02201-0RHR1GZ00120-1-2 © 2013 ROHM Co., Ltd. All rights reserved. 18.Apr.2016 Rev.003 www.rohm.com TSZ22111・15・001 Timing chart Figure 7. Timing chart 1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the DATA pin. 2. Parallel outputs (P1 to P8) are set to the shift register data after the eighth clock by the STB. 3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB. [ Function Explanation] ・ A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch circuit is reset non-synchronously without the other input condition, and all parallel outputs change into “L”. ・ A serial data inputted from DATA terminal is read in shift register with synchronized rising transition of clock. In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and outputs from the parallel data output terminal (P1 to P8). In case of STB is “H”, all parallel outputs and the data of latch do not change. [ Truth Table] Input Function CLK STB CLR × × L All the data of the latch circuit are set to “L” (data of shift register does not change), all the parallel outputs are “L”. H H Serial data of DATA pin are latched to the shift register. At this time, the data of the latch circuit does not change. L L H The data of the shift register are transferred to the latch circuit, and the data of the latch circuit are outputted from the parallel output pin. H The data of the shift register shifts 1bit, and the data of the latch circuit and parallel output also change. STB P1 to P8 Previous DATA DATA CLR “L” CLK DATA DATA8 DATA7 DATA6 DATA2 DATA1 |
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