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LM1972N bảng dữ liệu(PDF) 6 Page - National Semiconductor (TI) |
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LM1972N bảng dữ liệu(HTML) 6 Page - National Semiconductor (TI) |
6 / 11 page Application Information (Continued) INPUT IMPEDANCE The input impedance of a µPot is constant at a nominal 40 k Ω. To eliminate any unwanted DC components from propagating through the device it is common to use 1 µF in- put coupling caps. This is not necessary, however, if the dc offset from the previous stage is negligible. For higher per- formance systems, input coupling caps are preferred. OUTPUT IMPEDANCE The output of a µPot varies typically between 25 k Ω and 35 k Ω and changes nonlinearly with step changes. Since a µPot is made up of a resistor ladder network with a logarith- mic attenuation, the output impedance is nonlinear. Due to this configuration, a µPot cannot be considered as a linear potentiometer, but can be considered only as a logarithmic attenuator. It should be noted that the linearity of a µPot cannot be mea- sured directly without a buffer because the input impedance of most measurement systems is not high enough to provide the required accuracy. Due to the low impedance of the mea- surement system, the output of the µPot would be loaded down and an incorrect reading will result. To prevent loading from occurring, a JFET input op amp should be used as the buffer/amplifier. The performance of a µPot is limited only by the performance of the external buffer/amplifier. MUTE FUNCTION One major feature of a µPot is its ability to mute the input sig- nal to an attenuation level of 104dB as shown in Figure 3. This is accomplished internally by physically isolating the output from the input while also grounding the output pin through approximately 2 k Ω. The mute function is obtained during power-up of the device or by sending any binary data of 01111111 and above (to 11111111) serially to the device. The device may be placed into mute from a previous attenuation setting by sending any of the above data. This allows the designer to place a mute button onto his system which could cause a microcontroller to send the appropriate data to a µPot and thus mute any or all channels. Since this function is achieved through soft- ware, the designer has a great amount of flexibility in config- uring the system. DC INPUTS Although the µPot was designed to be used as an attenuator for signals within the audio spectrum, the device is capable of tracking an input DC voltage. The device will track DC voltages to a diode drop above each supply rail. One point to remember about DC tracking is that with a buffer at the output of the µPot, the resolution of DC tracking will depend upon the gain configuration of that output buffer and its supply voltage. It should also be remembered that the output buffer’s supply voltage does not have to be the same as the µPot’s supply voltage. This could allow for more reso- lution when DC tracking. SERIAL DATA FORMAT The LM1972 uses a 3-wire serial communication format that is easily controlled by a microcontroller. The timing for the 3-wire set, comprised of DATA-IN, CLOCK, and LOAD/ SHIFT is shown in Figure 2. Figure 9 exhibits in block dia- gram form how the digital interface controls the tap switches which select the appropriate attenuation level. As depicted in Figure 2, the LOAD/SHIFT line is to go low at least 150 ns before the rising edge of the first clock pulse and is to remain low throughout the transmission of each set of 16 data bits. The serial data is comprised of 8 bits for channel selection and 8 bits for attenuation setting. For both address data and attenuation setting data, the MSB is sent first and the 8 bits of address data are to be sent before the 8 bits of attenuation data. Please refer to Figure 7 to confirm the serial data for- mat transfer process. TABLE 1. LM1972 Micropot Attenuator Register Set Description MSB: LSB Address Register (Byte 0) 0000 0000 Channel 1 0000 0001 Channel 2 0000 0010 Channel 3 Data Register (Byte 1) Contents Attenuation Level dB 0000 0000 0.0 0000 0001 0.5 0000 0010 1.0 0000 0011 1.5 ::::: :: 0001 1110 15.0 0001 1111 15.5 0010 0000 16.0 0010 0001 16.5 0010 0010 17.0 ::::: :: 0101 1110 47.0 0101 1111 47.5 0110 0000 48.0 0110 0001 49.0 0110 0010 50.0 ::::: :: 0111 1100 76.0 0111 1101 77.0 0111 1110 78.0 0111 1111 100.0 (Mute) 1000 0000 100.0 (Mute) ::::: :: DS011978-9 FIGURE 6. Mono Panning Circuit www.national.com 6 |
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