công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
LM1972 bảng dữ liệu(PDF) 7 Page - National Semiconductor (TI) |
|
|
LM1972 bảng dữ liệu(HTML) 7 Page - National Semiconductor (TI) |
7 / 11 page Application Information (Continued) TABLE 1. LM1972 Micropot Attenuator Register Set Description (Continued) MSB: LSB Data Register (Byte 1) 1111 1110 100.0 (Mute) 1111 1111 100.0 (Mute) µPot SYSTEM ARCHITECTURE The µPot’s digital interface is essentially a shift register, where serial data is shifted in, latched, and then decoded. As new data is shifted into the DATA-IN pin, the previously latched data is shifted out the DATA-OUT pin. Once the data is shifted in, the LOAD/SHIFT line goes high, latching in the new data. The data is then decoded and the appropriate switch is activated to set the desired attenuation level for the selected channel. This process is continued each and every time an attenuation change is made. Each channel is up- dated, only, when that channel is selected for an attenuator change or the system is powered down and then back up again. When the µPot is powered up, each channel is placed into the muted mode. µPot LADDER ARCHITECTURE Each channel of a µPot has its own independent resistor lad- der network. As shown in Figure 8, the ladder consists of multiple R1/R2 elements which make up the attenuation scheme. Within each element there are tap switches that se- lect the appropriate attenuation level corresponding to the data bits in Table 1. It can be seen in Figure 8 that the input impedance for the channel is a constant value regardless of which tap switch is selected, while the output impedance varies according to the tap switch selected. DIGITAL LINE COMPATIBILITY The µPot’s digital interface section is compatible with either TTL or CMOS logic due to the shift register inputs acting upon a threshold voltage of 2 diode drops or approximately 1.4V. DIGITAL DATA-OUT PIN The DATA-OUT pin is available for daisy-chain system con- figurations where multiple µPots will be used. The use of the daisy-chain configuration allows the system designer to use only one DATA and one LOAD/SHIFT line per chain, thus simplifying PCB trace layouts. In order to provide the highest level of channel separation and isolate any of the signal lines from digital noise, the DATA-OUT pin should be terminated througha2k Ω resistor if not used. The pin may be left floating, however, any signal noise on that line may couple to adjacent lines creating higher noise specs. DS011978-10 FIGURE 7. Serial Data Format Transfer Process DS011978-12 FIGURE 8. µPot Ladder Architecture www.national.com 7 |
Số phần tương tự - LM1972 |
|
Mô tả tương tự - LM1972 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |