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MC100EPT26 bảng dữ liệu(PDF) 2 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator
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MC100EPT26
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2
1
2
3
45
6
7
8
Q0
GND
VCC
Figure 1. 8-Lead Pinout and Logic Diagram
D
Q1
D
VBB
NC
LVTTL
LVPECL
(Top View)
Table 1. PIN DESCRIPTION
Pin
Function
Q0, Q1
LVTTL Outputs
D0**, D1**
Differential LVPECL Inputs Pair
VCC
Positive Supply
VBB
Output Reference Voltage
GND
Ground
NC
No Connect
EP
(DFN8 only) Thermal exposed pad must be con-
nected to a sufficient thermal conduit. Electric-
ally connect to the most negative supply (GND)
or leave unconnected, floating open.
** Pins will default to VCC/2 when left open.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
50 kW
Internal Input Pullup Resistor
50 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb-Free Pkg
SOIC−8 NB
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
117 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.


Số phần tương tự - MC100EPT26_16

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