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MC100EP91MNG bảng dữ liệu(PDF) 7 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  Any Level Positive Input to NECL Output Translator
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Application Information
All MC100EP91 inputs can accept LVPECL, LVTTL,
LVCMOS, HSTL, CML, or LVDS signal levels. The
limitations for differential input signal (LVDS, HSTL,
LVPECL, or CML) are the minimum input swing of 150 mV
and the maximum input swing of 3.0 V. Within these
conditions, the input voltage can range from VCC to GND.
Examples interfaces are illustrated below in a 50
W
environment (Z = 50
W).
VEE
GND
GND
VEE
Z
Z
VCC
VCC
GND
LVPECL
Driver
EP91
50 W
VTT = VCC − 2.0 V
50 W
D
D
VCC
VCC
LVDS
Driver
EP91
Z
Z
D
D
100 W
Figure 6. Standard LVPECL Interface
Z
Z
VCC
VCC
HSTL
Driver
EP91
50 W 50 W
D
D
GND
Z
Z
VCC
VCC
CML
Driver
EP91
50 W
VCC
50 W
D
D
Figure 7. Standard LVDS Interface
Figure 8. Standard HSTL Interface
Figure 9. Standard 50 W Load CML Interface
GND
VEE
GND
GND
VEE
GND
GND
VEE
GND
VEE
GND
GND
Z
VCC
VCC
LVTTL
Driver
EP91
D
D
1.5 V
Figure 10. Standard LVTTL Interface
Z
VCC
VCC
LVCMOS
Driver
EP91
D
D
Open
Figure 11. Standard LVCMOS Interface
(D will default to VCC/2 when left open.
A reference voltage of VCC/2 should be applied
to D input, if D is interfaced to CMOS signals)
GND
(externally generated
reference voltage)


Số phần tương tự - MC100EP91MNG

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   2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
August, 2006 ??Rev. 1
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