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LMX2491RTWR bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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LMX2491RTWR bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 31 page 11 LMX2491 www.ti.com SNAS711 – OCTOBER 2016 Product Folder Links: LMX2491 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table 7. Register Descriptions of Ramp Comparators and Limits TYPE PROGRAMMING BIT THRESHOLD Ramp Limits RAMP_LIMIT_LOW Lower Limit RAMP_LIMIT_HIGH Upper Limit Ramp Comparators RAMP_CMP0 RAMP_CMP1 For the ramp comparators, if the ramp is increasing and exceeds the value as specified by RAMP_CMPx, then the flag goes high, otherwise it is low. If the ramp is decreasing and goes below the value as specified by RAMP_CMPx, then the flag goes high, otherwise it is low. 7.3.12 Power-on-reset (POR) The power-on-reset circuitry sets all the registers to a default state when the device is powered up. This same reset can be done by programming SWRST=1. In the programming section, the power on reset state is given for all the programmable fields. 7.4 Device Functional Modes The two primary ways to use the LMX2491 are to run it to generate a set of frequencies 7.4.1 Continuous Frequency Generator In this mode, the LMX2491 generates a single frequency that only changes when the N divider is programmed to a new value. In this mode, the RAMP_EN bit is set to 0 and the ramping controls are not used. The fractional denominator can be programmed to any value from 1 to 16777216. In this kind of application, the PLL is tuned to different channels, but at each channel, the goal is to generate a stable fixed frequency. 7.4.1.1 Integer Mode Operation In integer mode operation, the VCO frequency needs to be an integer multiple of the phase detector frequency. This can be the case when the output frequency or frequencies are nicely related to the input frequency. As a rule of thumb, if this an be done with a phase detector of as high as the lesser of 10 MHz or the OSCin frequency, then this makes sense. To operate the device in integer mode, disable the fractional circuitry by programming the fractional order (FRAC_ORDER), dithering (FRAC_DITH), and numerator (FRAC_NUM) to zero. 7.4.1.2 Fractional Mode Operation In fractional mode, the output frequency does not need to be an integer multiple of the phase detector frequency. This makes sense when the channel spacing is more narrow or the input and output frequencies are not nicely related. There are several programmable controls for this such as the modulator order, fractional dithering, fractional numerator, and fractional denominator. There are many trade-offs with choosing these, but here are some guidelines Table 8. Fractional Mode Register Descriptions and Recommendations PARAMETER FIELD NAME HOW TO CHOOSE Fractional Numerator and Denominator FRAC_NUM FRAC_DEN The first step is to find the fractional denominator. To do this, find the frequency that divides the phase detector frequency by the channel spacing. For instance, if the output ranges from 5000 to 5050 in 5-MHz steps and the phase detector is 100 MHz, then the fractional denominator is 100 MHz/5 = 20. So for a an output of 5015 MHz, the N divider would be 50 + 3/20. In this case, the fractional numerator is 3 and the fractional denominator is 20. Sometimes when dithering is used, it makes sense to express this as a larger equivalent fraction. Note that if ramping is active, the fractional denominator is forced to 224. Fractional Order FRAC_ORDER There are many trade-offs, but in general try either the 2nd or 3rd-order modulator as starting points. The 3rd-order modulator may give lower main spurs, but may generate others. Also if dithering is involved, it can generate phase noise. Dithering FRAC_DITH Dithering can reduce some fractional spurs, but add noise. Consult application note AN-1879 Fractional N Frequency Synthesis for more details on this. |
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