3

Common Start

Stop1

Stop2

Stop1

t1

t2

t1

Second Acquisition

Channel 1

Channel 2

Channel 6

t3

t1

t2

Stop1

Stop2

Stop3

Stop1

Stop2

t1

t2

First Acquisition

Start 2

Start 1

Figure 1. Multiacquisition, 6 channels, common start, multistop

Exceptional Performance for Precise Timing-

Measurement Applications

The Agilent Acqiris U1051A (TC890) features six indepen-

dent stopwatches for precise timing measurements from

a common start event to multiple stop events at a high

resolution.

The U1051A is ideal for time measurement applications in-

cluding LIDAR for 3D mapping and navigation, fluorescence

lifetime spectrometry and ion counting in time-of-flight

mass spectrometry (TOFMS). Many pulse timing measure-

ments, such as period, frequency and time interval analysis

(TIA), also benefit from the new TDC’s precise measure-

ment technology.

The U1051A CompactPCI module records multiple events or

hits on each of its six input channels, with a timing resolu-

tion of 50 ps and a mean dead time between sequential

pulses on the same input (double pulse resolution) of less

than 15 ns. Running at full speed, the U1051A offers a mas-

sive 25 million events-per-second data-throughput rate. The

U1051A enables event counting or histogram creation for

easy data and spectra comparison.

Six of the seven identical input channels are independent

stop inputs and the seventh is the common start. The

module operates in a multistart, multistop acquisition mode

with the timing information of stop events on all indepen-

dent channels encoded relative to the most recent start

event on the common channel.

In standard mode, the recording range is up to

10 ms. If one channel can be dedicated

to a fiducial signal, the 10 ms recording

time can be extended to a much wider

range. The large internal buffer allows

the recording of up to four million stop-

events per module.

On-Board Timing Calculation with Fast Data

Readout

The timing information of the start and hit events on all

channel inputs is obtained by combining a coarse-grain

(5 ns) wide-range (21 bit) real-time counter with a much

finer-grained interpolated result coming from the analysis

of a ramp signal started by the event.

Each channel consists of a programmable comparator, an

XOR gate used to select the active slope, a stable signal

generator, and an analog-to-digital converter (ADC). Once

digitized, the data are fed to a Xilinx Virtex-2 Pro FPGA-

based data processing unit for processing, storage, and

readout.

Data readout is achieved with a fast direct memory access

(DMA) mode at up to 100 MB/s.

Each channel is processed to determine the time of each

detected event, start and stop. The final relative time value

is obtained by subtracting the start time from each stop

time.

An additional auxiliary input for a common veto signal can

be used to enable/disable all start and stop detection, as

desired.