SN65MLVD080

SN65MLVD082

SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003

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5

DRIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tpLH

Propagation delay time, low-to-high-level output

1

1.5

2.4

ns

tpHL

Propagation delay time, high-to-low-level output

1

1.5

2.4

ns

tr

Differential output signal rise time

1

2

ns

tf

Differential output signal fall time

See Figure 5

1

2

ns

tsk(o)

Output skew

See Figure 5

350

ps

tsk(p)

Pulse skew (|tpHL − tpLH|)

0

150

ps

tsk(pp)

Part-to-part skew

600

ps

tjit(per)

Period jitter, rms (1 standard deviation) (2)

100 MHz clock input(3)

4

ps

tjit(c−c)

Cycle-to-cycle jitter, rms

100 MHz clock input(3)

45

ps

tjit(det)

Deterministic jitter

200 Mbps 215−1 PRBS input(4)

150

ps

tjit(pp)

Peak-to-peak jitter(2)(5)

200 Mbps 215−1 PRBS input(4)

190

ps

tpZH

Enable time, high-impedance-to-high-level output

7

ns

tpZL

Enable time, high-impedance-to-low-level output

See Figure 6

7

ns

tpHZ

Disable time, high-level-to-high-impedance output

See Figure 6

7

ns

tpLZ

Disable time, low-level-to-high−impedance output

7

ns

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

(2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(3) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.

(4) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.

(5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).