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5 / 30 page ADM1024 www.onsemi.com 5 Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1 and 2)) Parameter Unit Max Typ Min Test Conditions/Comments OPEN-DRAIN SERIAL DATABUS OUTPUT (SDA) Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 2.85 V −3.60 V − − 0.4 V High Level Output Leakage Current, IOH VOUT = VCC − 0.1 100 mA SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.2 − − V Input Low Voltage, VIL − − 0.8 V Hysteresis − 500 − mV Glitch Immunity − 100 − ns DIGITAL INPUT LOGIC LEVELS (ADD, CI, RESET, VID0−VID4, FAN1, FAN2) (Note 7) Input High Voltage, VIH VCC = 2.85 V − 5.5 V 2.2 − − V Input Low Voltage, VIL VCC = 2.85 V − 5.5 V − − 0.8 V NTEST_IN Input High Current, IIH VCC = 2.85 V − 5.5 V 2.2 − − V DIGITAL INPUT CURRENT Input High Current, IIH VIN = VCC –1.0 − − mA Input Low Current, IIL VIN = 0 − − 1.0 mA Input Capacitance, CIN − 20 − pF SERIAL BUS TIMING (Note 8) Clock Frequency, fSCLK See Figure 2 − − 400 kHz Glitch Immunity, tSW See Figure 2 − − 50 ns Bus Free Time, tBUF See Figure 2 1.3 − − ms Start Setup Time, tSU; STA See Figure 2 600 − − ns Start Hold Time, tHD; STA See Figure 2 600 − − ns SCL Low Time, tLOW See Figure 2 1.3 − − ms SCL High Time, tHIGH See Figure 2 0.6 − − ms SCL, SDA Rise Time, tr See Figure 2 − − 300 ns SCL, SDA Fall Time, tf See Figure 2 − − 300 ms Data Setup Time, tSU; DAT See Figure 2 100 − − ns Data Hold Time, tHD; DAT See Figure 2 − − 900 ns 1. All voltages are measured with respect to GND, unless otherwise specified. 2. Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V. 3. TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including an external series input protection resistor value between 0 k W and 1 kW. 4. Total monitoring cycle time is nominally m × 755 ms + n × 33244 ms, where m is the number of channels configured as analog inputs, plus 2 for the internal VCC measurement and internal temperature sensor, and n is the number of channels configured as external temperature channels (D1 and D2). 5. The total fan count is based on two pulses per revolution of the fan tachometer output. 6. Open−drain digital outputs may have an external pullup resistor connected to a voltage lower or higher than VCC (up to 6.5 V absolute maximum). 7. All logic inputs except ADD are tolerant of 5.0 V logic levels, even if VCC is less than 5.0 V. ADD is a three-state input that may be connected to VCC, GND, or left open−circuit. 8. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge. Figure 2. Serial Bus Timing Diagram P S PS SCL SDA tR tF tLOW tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA tHD:STA tSU:STO tBUF |
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