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LC78616PE bảng dữ liệu(PDF) 2 Page - ON Semiconductor

tên linh kiện LC78616PE
Giải thích chi tiết về linh kiện  Digital Servo Processor LSI
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nhà sản xuất  ONSEMI [ON Semiconductor]
Trang chủ  http://www.onsemi.com
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LC78616PE bảng dữ liệu(HTML) 2 Page - ON Semiconductor

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Detail of Functions
[CD-DSP functions]
< Playback functions>
 Playback mode : CLV playback / Jitter free playback (VCEC)
 Playback speed : Normal speed, double speed, quadruple speed (CLV playback / Jitter free playback)
<RF processing block>
 RF system
: AGC, CD-R and CD-R/W playback support, peak hold, bottom hold
 Error system
: TE signal generation, FE signal generation
 Detection
: Track count signal, Jitter, Defect (black, mirror)
 LASER power controller (APC)
 DC offset voltage cancellation
<Servo control block>
 All servo systems as tracking, focus, sled and spindle are implemented with digital processing.
 Automatic adjustment functions : focus gain, focus bias, focus offset, tracking gain, tracking offset and
tracking balance
 Shock detection / Interruption detection
<CD signal processing block>
 EFM signal synchronization detection, protection and interpolation
 Error detection, correction (C1 = double, C2 = quadruple/double)
 Jitter margin ±19 frames
<CD-TEXT processing block>
 Buffers CD-TEXT decoded data to the buffer memory.
 Starts buffering of CD-TEXT decoded data from desired ID3/ID4.
<Shock proof processing block>
 Shock proof processing using with external 16M-bit or 64M-bit Memory
Approximately 10sec. with 16Mbit or 40sec. with 64Mbit
[CD data processing functions]
<CDDA data processing block>
 Interpolation
 Mute function (
12 dB, ∞)
 Digital attenuator
 De-emphasis filter
<CDROM data processing block>
 CLV playback
: Fixed normal speed or double speed
 Jitter free playback (VCEC) : Free speed within quadruple speed
*CDROM Data is not buffering to SDRAM and output directly
<Outputs format>
 Digital 3 lines output(LRCK,BCK,DATA)
 Supports various external audio data output format
IIS (48 fs), MSB First, Right-Justified, Left-Justified (32 fs / 48 fs), 16-bit data length
 Slave mode
Output DATA synchronized to external Clock input (LRCK and BCK)
 Digital output (S/PDIF, only CLV playback mode)
[Internal Microcontroller functions]
<Sequencer control>
 CD playback control
Servo control, CD-TEXT processing, Digital data output control, etc.
<Communication control between main controller>
 The SIO interface using CE, CL, DI, DO and BUSYB pins is available as communication format.
 External main controller can control this IC directly such as “stop oscillation” or “restart oscillation” or so
on at the internal register open mode (REG_READY high condition).
 Even while the oscillation is stopped, some of general port can be controlled by host controller.
<Peripheral interface block>
 GPIO port 8 ports maximum (Shared with other functions.)
<Program memory block>
 Mask-ROM type
 ROM Correct function is built in for the partial change of the program and Host controller can use this.
<Others>
 Watch Dog Timer
Notifies to outside from a pin or resets internally.
 Power management (Two kinds of sleep mode)
(1) Only the clock for CPU core is operating and clocks for other blocks are stopping.
(2) All clocks are stopping.
[Others]
<Internal power supply>
 1.5 V regulator for internal blocks


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