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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADS1148QPWRQ1 bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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ADS1148QPWRQ1 bảng dữ liệu(HTML) 9 Page - Texas Instruments |
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9 / 80 page  9 ADS1148-Q1 www.ti.com SBAS674A – JULY 2014 – REVISED SEPTEMBER 2016 Product Folder Links: ADS1148-Q1 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) tCLK = 1 / fCLK. The default clock frequency fCLK = 4.096 MHz. (2) Applicable only when fCLK = 4.096 MHz, scales proportionally with fCLK frequency. 6.6 Timing Requirements at TA = –40°C to +125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted) MIN NOM MAX UNIT SERIAL INTERFACE (See Figure 1 and Figure 2) tCSSC Delay time, first SCLK rising edge after CS falling edge 10 ns tSCCS Delay time, CS rising edge after final SCLK falling edge 7 tCLK (1) tCSPW Pulse duration, CS high 7 tCLK tSCLK SCLK period 488 ns 64 Conversions tSPWH Pulse duration, SCLK high 0.3 0.7 tSCLK tSPWL Pulse duration, SCLK low 0.3 0.7 tSCLK tDIST Setup time, DIN valid before SCLK falling edge 25 ns tDIHD Hold time, DIN valid after SCLK falling edge 25 ns tSTD Setup time, SCLK low before DRDY rising edge 7 tCLK tDTS Delay time, SCLK rising edge after DRDY falling edge 1 tCLK MINIMUM START TIME PULSE DURATION (See Figure 3) tSTART Pulse duration, START high 3 tCLK RESET PULSE DURATION, SERIAL INTERFACE COMMUNICATION AFTER RESET (See Figure 4) tRESET Pulse duration, RESET low 4 tCLK tRHSC Delay time, SCLK rising edge (start of serial interface communication) after RESET rising edge 0.6(2) ms 6.7 Switching Characteristics at TA = –40°C to +125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted); see Figure 1 and Figure 2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDOPD Propagation delay time, SCLK rising edge to valid new DOUT DVDD ≤ 3.6 V 50 ns DVDD > 3.6 V 180 tDOHD DOUT hold time 0 ns tCSDO Propagation delay time, CS rising edge to DOUT high impedance 25 ns tPWH Pulse duration, DRDY high 3 tCLK |
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