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ES1021QI bảng dữ liệu(PDF) 8 Page - Altera Corporation |
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ES1021QI bảng dữ liệu(HTML) 8 Page - Altera Corporation |
8 / 14 page Page 8 Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation If some of the rails are sequenced together to reduce cost and eliminate the effect of capacitor variance on the timing, a common capacitor can be connected to two or more DLY_ON or DLY_OFF pins. In this case, multiply the capacitor value by the number of common DLY_X pins to obtain the desired timing. Table 1 shows the nominal time delay on the DLY_X pins for various capacitor values, from the start of charging to the 1.27V reference. This table does not include the 10ms of ENABLE lockout delay during a start-up sequence, but it does represent the time from the end of the ENABLE lockout delay to the start of GATE transition. There is no ENABLE lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME(s) Open 0.00006 100pF 0.00013 1000pF 0.0013 0.01µF 0.013 0.1µF 0.13 1µF 1.3 10µF 13 NOTE: Nom. TDEL_SEQ = Capacitor (µF)*1.3MW. 10128 July 9, 2014 Rev A |
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Mô tả tương tự - ES1021QI |
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