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FDC37N769 bảng dữ liệu(PDF) 10 Page - SMSC Corporation |
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FDC37N769 bảng dữ liệu(HTML) 10 Page - SMSC Corporation |
10 / 138 page SMSC DS – FDC37N769 Page 10 of 137 Rev. 12/21/2000 TQFP PIN # NAME SYMBOL BUFFER TYPE DESCRIPTION 81,91 nData Terminal Ready nDTR1 nDTR2 O6 Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. 80,90 nClear to Send nCTS1 nCTS2 I Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. 78,88 nData Set Ready nDSR1 nDSR2 I Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. 83,85 nData Carrier Detect nDCD1 nDCD2 I Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. 82,84 nRing Indicator nRI1 nRI2 I (Note 1) Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. TQFP PIN # NAME SYMBOL BUFFER TYPE DESCRIPTION PARALLEL PORT INTERFACE (NOTE 2) 71 nPrinter Select Input/FDC nStep Pulse (Note 3) nSLCTIN nSTEP (OD14/OP1 4)/OD12 This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. |
Số phần tương tự - FDC37N769 |
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Mô tả tương tự - FDC37N769 |
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