NRND

TP3404

SNOS703 – DECEMBER 2004

www.ti.com

ACTIVATION AND LOOP SYNCHRONIZATION

Activation (i.e. power-up and loop synchronization) may be initiated from either end of the loop. If the master

(QDASL) end is activating the loop, it sends normal bursts of scrambled “1”s which are detected by the slave's

line-signal-detect circuitry. The slave then replies with bursts of scrambled “1”s synchronized to the received

bursts, and the Framing Detection circuit at each end searches for 4 consecutive correctly formatted receive

bursts to acquire full loop synchronization. The QDASL receiver indicates when it is correctly in sync with

received bursts by setting an indication in the Status Register and pulling the INT pin low.

For the slave end to initiate activation, it begins transmission of alternate bursts i.e., the burst repetition rate is 2

kHz, not 4 kHz. At this point the slave is running from its local oscillator and is not receiving any sync information

from the master. When the master's Line-Signal Detect Circuit recognizes this “wake-up” signal, the appropriate

QDASL line must be activated by writing to the Control Register. The master begins to transmit bursts

synchronized, as normal, to the FS input with a 4 kHz repetition rate. This enables the slave's receiver to

correctly identify burst timing from the master and to re-synchronize its own burst transmissions to those it

receives. The Framing Detection Circuits then acquire full loop sync as described earlier.

Loop synchronization is considered to be lost if the Framing Detection Circuit does not find four framing marks of

the four consecutive 4 kHz line frames. At this point an indication is set in the Status Register, the INT output is

pulled low, and the receiver searches to re-acquire loop sync.

MICROWIRE CONTROL INTERFACE

A serial interface, which can be clocked independently from the B and D channel system interfaces, is provided

for microcontroller access to the time-slot assignment, Control and Status Registers in the QDASL. The

microcontroller is normally the timing master of this interface, and it supplies the CCLK and CS signals.

All data transfers consist of simultaneous read and write cycles, in which 2 continuous bytes are sampled on the

CI pin, at the same time as 2 bytes are shifted out from the CO pin, see Figure 7. The first byte is a register

address and the second is the data. To initiate a Microwire read/write cycle, CS must be pulled low for 16 cycles

of CCLK. Data on CI is sampled on rising edges of CCLK, and shifted out from CO on failing edges. When CS is

high, the CO pin is in the high-impedance TRI-STATE, enabling the CO pins of many devices to be multiplexed

together.

Whenever a change (except Bipolar Violation) in any of the QDASL status conditions occurs, the Interrupt output

INT is pulled low to alert the microprocessor to initiate a read cycle of the Status Register. This latched output is

cleared when the read cycle is initiated.

Table 1 lists the address map of control functions and status indicators. Table 2 lists the addresses for the

Control Registers for each QDASL line. Even-numbered addresses are read-write cycles, in which the data

returned by the CO pin is previous contents of the addressed register. Odd-numbered addresses are readback

commands only.

Table 1. Global Register Address Map

Address

Registers

(Hex)

00–0F

LINE 0 Control (TSX,TSR,CTRL)

10–1F

LINE 1 Control (TSX,TSR,CTRL)

20–2F

LINE 2 Control (TSX,TSR,CTRL)

30–3F

LINE 3 Control (TSX,TSR,CTRL)

40–CF

Not used

FF

Common Status Register for all lines (0–3).

See Table 6

8

Submit Documentation Feedback

Copyright © 2004, Texas Instruments Incorporated

Product Folder Links: TP3404