TP3094_12 datasheet(4/20 Pages) TI1

tên linh kiện	TP3094

Giải thích chi tiết về linh kiện	Handles four voice channels

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expects its individual transmit and receive frame

signal. When it is HIGH, the 32 bit mode is select-

ed; in this mode FSX0 and FSR0 are used as

framing signals and the TS are allocated consec-

utively from these frames, starting from Ch0 to

Ch3. In this mode FSX1 and FSR1 become out-

puts and produce 1 bit long frame signals with the

last bit of the 32 bit stream. These Frame signals

can be used to cascade another device in 32 bit

mode.

NF

Noise Filter Pin. For optimal noise rejection a

100nF capacitor must be connected between this

pin and the analog ground AGND0.

PT1, PT2, PT3, PT4 (inputs)

These pins are used by National for internal man-

ufacturing test. They must be connected to digital

ground for normal device operation.

NC

All NC pins must be connected to nearest analog

ground, to reduce the device noise sensitivity.

Functional Description

The TP3094 performs the complete CODEC/filter

functions for four voice channels using a digital

signal processing architecture. MCLK provides

the clock reference to the whole circuitry and the

bit clock for the PCM bus. Its value can be either

8.192MHz,

4.096MHz,

2.048MHz

or

1.536/

1.544MHz, and it is automatically selected inter-

nally. The TP3094 handles the conversion be-

tween the analog signals on the subscriber line

and the PCM data samples on a PCM highway.

Digital filters are used to band-limit the voice sig-

nals.

The device can work in a 8 bit mode where each

channel has an independently selected Time

Slot, or in the 32 bit mode, where the four chan-

nels use four consecutive Time Slots. The time-

division multiplexed PCM data is transferred to

the PCM highway through the standard serial

PCM bus.

Each channel has its dedicated Power Down in-

put.

Power Initialization

When power is first applied to the device, power-

on reset circuitry initializes the device and places

it in the power down state. All non-essential cir-

cuits are de-activated. PCM output DX and ana-

log outputs VRO0-3 are placed in the high

impedance state, while FSX1 and FSR1 outputs

are held low (in case 32-bit mode is selected). In

the power down mode, power consumption is re-

duced to a minimum, typically 2mW. The device

will remain in this state as long as no MCLK is ap-

plied and no Frame Signal is applied (just FSX0

and FSR0 in case of 32-bit mode).

For each channel, when the PDN input is not ac-

tive, MCLK is applied, and a FS (receive or trans-

mit) pulse is running, the device enters the active

power up mode. The MCLK frequency is detected

with any available FS signal; the clock rate detec-

tion may last for up to 4ms, after which the device

is ready for powering up. Analog and PCM output

signals will be available after a few frames; it will

take about 100ms until the first activated channel

is fully functional.

The device will only power up when at least one

of the FS signals and the MCLK signal are in a

valid frequency ratio.

Power Down and Reset

When one channel is in Power Down Mode, the

DX output will remain in high impedance state

and the input on the DR will be ignored when its

FS signal is active; the analog output VRO will be

in high impedance.

Each channel will enter the power down mode

when at least one of the following conditions oc-

curs

• The PDN signal is active for more than 16

MCLK cycles (and TST is not active at the

same time)

• More than 4 pulses of the respective FS are

missing.

• MCLK is missing for a 12us.

When the PDN input is active (HIGH) for at least

16 MCLK clock cycles, the channel will go into

power down mode and reset its state within a

frame sync. The channel will recover from Power

Down, after having detected the PDN signal inac-

tive (LOW) for at least 16 MCLK clock cycles and

after 1 frame sync pulse.

This power down mode will work only in presence

of the master clock at the pin MCLK.

Pin Descriptions (continued)

Số phần tương tự - TP3094_12

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