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VNH3SP30 bảng dữ liệu(PDF) 9 Page - STMicroelectronics |
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VNH3SP30 bảng dữ liệu(HTML) 9 Page - STMicroelectronics |
9 / 26 page 9/26 VNH3SP30 TEST MODE The PWM pin allows to test the load connection between two half-bridges. In the test mode (Vpwm=-2V) the internal Power Mos gate drivers are disabled. The INA or INB inputs allow to turn-on the High Side A or B, respectively, in order to connect one side of the load at VCC voltage. The check of the voltage on the other side of the load allow to verify the continuity of the load connection. In case of load disconnection the DIADX/ENX pin corresponding to the faulty output is pulled down. ELECTRICAL TRANSIENT REQUIREMENTS ISO T/R 7637/1 Test Pulse Test Level I Test Level II Test Level III Test Level IV Test Levels Delays and Impedance 1 -25V -50V -75V -100V 2ms, 10 Ω 2 +25V +50V +75V +100V 0.2ms, 10 Ω 3a -25V -50V -100V -150V 0.1 µs, 50Ω 3b +25V +50V +75V +100V 0.1 µs, 50Ω 4 -4V -5V -6V -7V 100ms, 0.01 Ω 5 +26.5V +46.5V +66.5V +86.5V 400ms, 2 Ω ISO T/R 7637/1 Test Pulse Test Levels Result I Test Levels Result II Test Levels Result III Test Levels Result IV 1 CC C C 2 CC C C 3a CC C C 3b CC C C 4 CC C C 5 CE E E Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 1 |
Số phần tương tự - VNH3SP30 |
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Mô tả tương tự - VNH3SP30 |
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