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TMP124 bảng dữ liệu(PDF) 9 Page - Texas Instruments

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tên linh kiện TMP124
Giải thích chi tiết về linh kiện  1.5째C Accurate Programmable Digital Temperature Sensors with SPI Interface
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TMP124 bảng dữ liệu(HTML) 9 Page - Texas Instruments

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TMP122, TMP124
9
SBOS272B
www.ti.com
CONVERSION TIME
R1
R0
RESOLUTION
(typical)
0
0
9 Bits (0.5
°C) plus sign
30ms
0
1
10 Bits (0.25
°C) plus sign
60ms
1
0
11 Bits (0.125
°C) plus sign
120ms
1
1
12 Bits (0.0625
°C) plus sign
240ms
TABLE XI. Resolution of the TMP122 and TMP124.
CONVERTER RESOLUTION (R1/R0)
The Converter Resolution Bits control the resolution of the
internal Analog-to-Digital (A/D) converter. This allows the user
to maximize efficiency by programming for higher resolution or
faster conversion time. Table XI identifies the Resolution Bits
and the relationship between resolution and conversion time.
The TMP122/TMP124 have a default resolution of 12 bits.
DELAY TIME
The Delay Bits control the amount of time delay between each
conversion. This feature allows the user to maximize power
savings by eliminating unnecessary conversions, and minimiz-
ing current consumption. During active conversion the TMP122/
TMP124 typically requires 50
µA of current for approximately
0.25s conversion time, and approximately 20
µA for idle times
between conversions. Delay settings are identified in Table XII
as conversion time and period, and are shown in Figure 9.
Default power up is D1/D0 equal 0/0. Conversion time and
conversion periods scale with resolution. Conversion period
denotes time between conversion starts.
D1
D0
CONVERSION TIME
CONVERSION PERIOD
0
0
0.25s
0.25s
0
1
0.25s
0.5s
1
0
0.25s
1s
1
1
0.25s
8s
TABLE XII. Conversion Delay for 12-Bit Resolution.
FIGURE 9. Conversion Time and Period Description.
PARAMETER
MIN
MAX
UNITS
SCK Period
t1
100
ns
Data In to Rising Edge SCK Setup Time
t2
20
ns
SCK Falling Edge to Output Data Delay
t3
30
ns
SCK Rising Edge to Input Data Hold Time
t4
20
ns
CS to Rising Edge SCK Set-Up Time
t5
40
ns
CS to Output Data Delay
t6
30
ns
CS Rising Edge to Output High Impedance
t7
30
ns
TABLE XIII. Timing Description.
0.25s
D1/D0 = 0/1
D1/D0 = 1/0
D1/D0 = 1/1
12-Bit Resolution
0.25s
1s
8s
0.25s
0.5s
50
µA (active)
20
µA (idle)
Timing Diagrams
The TMP122/TMP124 are SPI compatible. Figures 10 to 12
describe the various timing parameters of the TMP122/
TMP124 with timing definitions in Table XIII.


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