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TL16C552FNRG4 bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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TL16C552FNRG4 bảng dữ liệu(HTML) 6 Page - Texas Instruments |
6 / 33 page TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of operating free-air temperature and supply voltage PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage IOH = − 0.4 mA for DB0 −DB7, IOH = − 2 mA for PD0 −PD7, IOH = − 0.4 mA for INIT, AFD, STB, and SLIN (see Note 2), IOH = − 0.4 mA for all other outputs 2.4 V VOL Low-level output voltage IOL = 4 mA for DB0 −DB7, IOL = 12 mA for PD0 −PD7, IOL = 10 mA for INIT, AFD, STB, and SLIN (see Note 2), IOL = 2 mA for all other outputs 0.4 V II Input current VDD = 5.25 V, All other terminals are floating ±10 µA II(CLK) Clock input current VI = 0 to 5.25 V ±10 µA VDD = 5.25 V, VO = 0 with chip deselected, or IOZ High-impedance output current VDD = 5.25 V, VO = 0 with chip deselected, or VO = 5.25 V with chip and write mode selected ±20 µA IOZ High-impedance output current DD O VO = 5.25 V with chip and write mode selected ±20 µA VDD = 5.25 V, No loads on outputs, IDD Supply current VDD = 5.25 V, No loads on outputs, SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1, 50 mA IDD Supply current SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1, RI0 and RI1 at 2 V, Other inputs at 0.8 V, 50 mA RI0 and RI1 at 2 V, Other inputs at 0.8 V, Baud rate generator fclock = 8 MHz, Baud rate = 56 kbit/s NOTE 2: These four terminals contain an internal pullup resistor to VDD of approximately 10 kΩ. clock timing requirements over recommended ranges of operating free-air temperature and supply voltage MIN MAX UNIT tw1 Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1) 55 ns tw2 Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1) 55 ns tw3 Pulse duration, master (RESET) low (see Figure 16) 1000 ns read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 4) MIN MAX UNIT tw4 Pulse duration, IOR low 80 ns tsu1 Setup time, chip select valid before IOR low (see Note 3) 15 ns tsu2 Setup time, A2 − A0 valid before IOR low (see Note 3) 15 ns th1 Hold time, A2 − A0 valid after IOR high (see Note 3) 20 ns th2 Hold time, chip select valid after IOR high (see Note 3) 20 ns td1 Delay time, tsu2 + tw4 + td2 (see Note 4) 175 ns td2 Delay time, IOR high to IOR or IOW low 80 ns NOTES: 3. The internal address strobe is always active. 4. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR). |
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