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LMH1983 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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LMH1983 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 55 page  LMH1983 SNLS309I – APRIL 2010 – REVISED DECEMBER 2014 www.ti.com Pin Functions (continued) PIN SIGNAL I/O DESCRIPTION LEVEL NO. NAME 13 NO_REF O LVCMOS Loss of reference status flag (active high) 14 CLKout4– Audio clock from PLL4 (fundamental rate is 98.304 MHz). O LVDS 15 CLKout4+ The output is 24.576 MHz by default and is selectable via the host. 16 VDD – Power 3.3 V supply for CLKout4 Audio frame timing signal for OUT4 (active low.) Timing Generator fixed to PLL4 clock. The output is the audio-video-frame (AVF) pulse by default and is programmable via the host. Optional OSCin function 17 Fout4 (OSCin) I/O LVCMOS can be used to apply a 27 MHz external clock for PLL4 to generate an audio clock independent of the video input reference; this function must be enabled via the host. 18 GND – GND Ground 19 VDD – Power 3.3 V supply for PLL3 and PLL4 20 VDD – Power 3.3 V supply for CLKout3 21 GND – GND Ground Video frame timing signal for OUT3 (active low). Timing generator 22 Fout3 O LVCMOS assignable to PLL1, PLL2, or PLL3. OUT3 format is selectable via the host. Video clock from PLL1, PLL2, or PLL3 depending on output 23 CLKout3+ O LVDS crosspoint mode. The output is 148.35 MHz by default and is 24 CLKout3– selectable via the host. Bias bypass for on-chip LDO for PLL3 25 Cbyp3 – Analog Connect to 1.0 µF and 0.1 µF bypass capacitors. Bias bypass for on-chip LDO for PLL4 26 Cbyp4 – Analog Connect to 1.0 µF and 0.1 µF bypass capacitors. Bias bypass for on-chip LDO for PLL2 27 Cbyp2 – Analog Connect to 1.0 µF and 0.1 µF bypass capacitors. Video clock from PLL1, PLL2, or PLL3 depending on output 28 CLKout2+ O LVDS crosspoint mode. The output is 148.5 MHz by default and is selectable 29 CLKout2– via the host. Video frame timing signal for OUT2 (active low). Timing generator 30 Fout2 O LVCMOS assignable to PLL1, PLL2, or PLL3. OUT2 format is selectable via the host. 31 VDD – Power 3.3-V supply for CLKout2 32 VDD – Power 3.3-V supply for PLL2 27 MHz VCXO clock signal for PLL1. 33 XOin– (3) – LVCMOS: Directly connect clock signal to XOin+ and bias XOin- to I LVCMOS/LVDS 34 XOin+ mid-supply with 0.1µF bypass capacitor. – LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.(4) 35 CLKout1– Video clock from PLL1. O LVDS 36 CLKout1+ The output is 27 MHz by default and is selectable via the host. Reference frame timing signal for OUT1 (active Low). Timing 37 Fout1 O LVCMOS generator fixed to PLL1 OUT1 Format follows the reference input format. 38 VDD – Power 3.3 V supply for CLKout1 39 GND – GND Ground Loop filter for PLL1 charge pump output with VCXO Voltage Control (VC) sensing. 40 VC_LPF O Analog If free-run and holdover mode, PLL1 is disabled and an internal DAC outputs a control voltage to the VCXO. – DAP – GND Die Attach Pad (Connect to ground on PCB) (3) XOin must be driven by a 27 MHz clock in order to read or write registers via I2C. (4) A TCXO or other clean 27 MHz oscillator can be applied for standalone clock generation using PLLs 2-4 (bypass PLL1). 4 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: LMH1983 |
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