LMH1983 datasheet(3/55 Pages) TI1

tên linh kiện	LMH1983

Giải thích chi tiết về linh kiện	3G/HD/SD Video Clock Generator with Audio Clock

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1

2

3

4

5

6

7

8

30

29

28

27

26

25

24

23

VDD

Vin

Fin

CLKout3+

Cbyp2

VDD

Hin

INIT

Fout2

CLKout2+

SDA

CLKout3-

9

SCL

10

22

21

Fout3

Cbyp3

CLKout2-

Die Attach Pad (DAP)

Connect to GND on PCB

ADDR

GND

Cbyp4

VDD

LMH1983

www.ti.com

SNLS309I – APRIL 2010 – REVISED DECEMBER 2014

5 Description (continued)

When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of

reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output

accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize

to a previous reference with glitch-less operation.

6 Pin Configurations and Functions

RTA40A Package

40-Pin WQFN Package with Exposed Thermal Pad

Top View

Pin Functions

SIGNAL

I/O

DESCRIPTION

LEVEL

NO.

NAME

1

VDD

–

Power

3.3-V supply for PLL1

2

VDD

–

Power

3.3-V supply for logic I/O

Horizontal sync reference signal

3

Hin

I

LVCMOS

Auto polarity correction for HVF will be based off Hin polarity.

Recognized clock inputs can be applied to Hin.

4

Vin

I

LVCMOS

Vertical sync reference signal

5

Fin

I

LVCMOS

Field sync (odd/even) reference signal

6

INIT

I

LVCMOS

Reset signal for audio-video phase alignment (rising edge triggered)

I2C address select

Pin settings:

7

ADDR

I

LVCMOS

– Tie low: 0x65 (7-bit slave address in hex)

– Float: 0x66

– Tie high: 0x67

8

SDA(1)

I/O

I2C

I2C Data signal

9

SCL(1)

I

I2C

I2C Clock signal

10

VDD

–

Power

3.3-V supply for logic I/O

11

NO_LOCK(2)

O

LVCMOS

Loss of lock status flag for PLLs 1-4 (active high)

12

NO_ALIGN

O

LVCMOS

Loss of alignment status flag for OUTs 1–4 (active high)

(1)

SDA and SCL pins each require a pull-up resistor of 4.7 k

Ω to the VDD supply.

(2)

The NO_LOCK status flag is derived from the Lock Status register bits (LOCK1-4) for each PLL. Each lock status bit can be masked

from the NO_LOCK flag by setting their respective mask bits.

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