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SN74V263-15PZA bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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SN74V263-15PZA bảng dữ liệu(HTML) 9 Page - Texas Instruments |
9 / 52 page SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 partial reset (PRS) A partial reset is accomplished when the PRS input is taken to a low state. As in the case of the master reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes low, PAF goes high, and HF goes high. Whichever mode is active at the time of partial reset remains selected (FWFT or standard mode). If FWFT mode is active, OR goes high and IR goes low. If the standard mode is active, FF goes high and EF goes low. Following partial reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) active at the time of partial reset also is retained. The output register is initialized to all zeroes. PRS is asynchronous. A partial reset is useful for resetting the device during operation, when reprogramming programmable-flag offset settings might not be convenient. See Figure 6 for timing information. retransmit (RT) The retransmit operation allows previously read data to be accessed again. There are two modes of retransmit operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup procedure that resets the read pointer to the first location of memory. The second stage is the actual retransmit, which consists of reading out the memory contents, starting at the beginning of the memory. Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before RCLK rises when RT is low. When zero latency is used, REN need not be high before RCLK rises while RT is low. If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes low, retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK. See Figure 12 for timing information. If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location in memory. Since standard mode is selected, every word read, including the first word following retransmit setup, requires a low on REN to enable the rising edge of RCLK. See Figure 11 for timing information. In retransmit operation, the zero-latency mode can be selected using the retransmit latency mode (RM) pin during a master reset. This can be applied to the standard mode and the FWFT mode. retransmit latency mode (RM) A zero-latency retransmit timing mode can be selected using RM. During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being low. See Figures 13 and 14 for timing information. |
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