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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LM98620 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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LM98620 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 69 page  LM98620 SNAS426C – FEBRUARY 2008 – REVISED MAY 2014 www.ti.com Pin Functions PIN PULLUP TYPE(1) DESCRIPTION PULLDOWN NAME NUMBER SHD/HOLD 1 DI Data Clamp Pulse/Hold Input VDDD 2, 15, 19, 54 PI Digital Power Supply VSSD 3, 14, 18, 55 PI Digital Power Supply Ground CLPIN 4 DI Input Pulse that Invokes the Input Clamp Switch BLKCLP 5 DI PD 108 k Ω Input Pulse that Invokes the Black Calibration Loop DI PU 108 k Ω Input Pulse that Invokes the White Calibration Loop. Tie high to disable AGC_ONB 6 White Clamp. Pulse Low to initiate White Clamp. (Active Low) DI Over Voltage Protection Enable (Active Low). Enables OS input OVPB 7 protections switches to ground during system power up. Should be tied high after AFE and CCD voltages have stabilized. MCLK 8 DI Master Clock Input GPI1-5 9 to 13 DI General Purpose Inputs 1 – 5, mapped into LVDS output data AO Optional IBIAS resistor connection. To minimize device to device power consumption variation, connect an 11k Ω 1% resistor to VSSA. If no IBIAS 16 resistor is used, the internal bias and power supply currents will be subject to normal device to device variation. VREG1 17, 46 PO Decoupling connection for VREG1 – Approx. 1.8 V output(2) Decoupling connection for VREG2 – Approx. 1.8 V output(2) VREG2 20, 27, 33, 43 PO TXCLK1 21, 22 DO Differential LVDS Output Clock 1 TXOUTC1 23, 24 DO Differential LVDS Output Data C1 TXOUTB1 25, 26 DO Differential LVDS Output Data B1 VSSLVDS 28, 34, 41, 42 PI LVDS Power Supply Ground TXOUTA1 29, 30 DO Differential LVDS Output Data A1 TXCLK2 31, 32 DO Differential LVDS Output Clock 2 TXOUTC2 35, 36 DO Differential LVDS Output Data C2 TXOUTB2 37, 38 DO Differential LVDS Output Data B2 TXOUTA2 39, 40 DO Differential LVDS Output Data A2 VDDLVDS 44, 45 PI LVDS Power Supply TESTO_1 47 DO Digital Test Output TESTO_0 48 DO Digital Test Output RESETB 49 DI PU 108 k Ω Master Reset Input(Active Low) SCLK 50 DI Serial Clock for the 4-wire Serial Interface SDI 51 DI Serial Data for the 4-wire Serial Interface SENB 52 DI PU 108 k Ω Serial Enable (Active Low) for the 4-wire Serial Interface SDO 53 DO Serial Output Data for the 4-wire Serial Interface 56, 65, 69, 73, PI VSSA Analog Power Supply Ground 77 VREF 57 AO Reference Voltage Bypass – Approx. 1.2 V output(2) VDDA 58, 67, 71, 75 PI Analog Power Supply AO Top Reference Bypass. Connect to bypass capacitors (see Applications VREFTOUT 59 and Implementation) and VREFTINx. – Approx. 2.23 V output.(2) (1) KEY: A – Analog, D – Digital, P – Power, I – Input, O – Output, PD – Pull-down resistor to VSSD. PU – Pull-up resistor to VDDD. (2) Voltages provided for debugging only. Not a guaranteed specification. 4 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: LM98620 |
Số phần tương tự - LM98620 |
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Mô tả tương tự - LM98620 |
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