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LM97937RMET bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LM97937RMET bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 80 page  VA3.3 + - SDO 80: 80: VA3.3 VA1.2 LM97937 www.ti.com SNVS990A – DECEMBER 2013 – REVISED JANUARY 2014 PIN NAME TYPE/DIAGRAM DESCRIPTION SPI Interface Serial Clock pin. Serial data is shifted into and out of the 53 SCLK device synchronous with this clock signal. Compatible with 1.2 – 3.3 V CMOS logic levels. SPI Interface Chip Select pin. When this signal is asserted, SCLK is used to clock the input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is 54 CSB high impedance and the input data is ignored. Active low. A 10 k Ω pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2 – 3.3 V CMOS logic levels. SPI Interface Data Input pin. Serial data is shifted into the device on this 47 SDI pin while the CSB signal is asserted. Compatible with 1.2 – 3.3 V CMOS logic levels. SPI Interface Data Output pin. Serial data is shifted out of the device on this pin during a read command while CSB is asserted. The output logic level is 48 SDO configurable as 1.2 V, 1.8 V, 2.5 V or 3.3 V. The output level MUST be configured after power up and before performing a read command. See the Register Map for configuration details. 3.3 V Analog Power Supply pin. This pin must be connected to a quiet 2, 13, 42 VA3.3 Supply Input Pin source and decoupled to AGND with a 0.1 μF and a 0.01 μF capacitor located close to the pin. 1.8 V Analog Power Supply pins. These pins must be connected to a quiet 7, 15, 20, 29, 51, 56 VA1.8 Supply Input Pin source and decoupled to AGND with a 0.1 μF and a 0.01 μF capacitor located close to each pin. 1.2 V Analog Power Supply pins. These pins must be connected to a quiet 8, 21, 30, 50 VA1.2 Supply Input Pin source and decoupled to AGND with a 0.1 μF and a 0.01 μF capacitor located close to each pin. 1.2 V Digital Power Supply pin. This pin must be connected to a quiet 26, 45 VD1.2 Supply Input Pin source and decoupled to AGND with a 0.1 μF and a 0.01 μF capacitor located close to each pin. Capacitive Bypassing pin for internally regulated 2.5 V supply. 41 BP2.5 Bypass Pins This pin must be decoupled to AGND with a 0.1 μF and a 10 uF capacitor located close to the pin. Analog Ground. 3, 6, 9, 12, 16, 19, 22, AGND Analog Ground Must be connected to a solid ground 31, 40, 49, 52, 55 reference plane under the device. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM97937 |
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