Ch 0

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

P0

N0

P1

N1

P2

N2

P3

N3

P4

N4

P5

N5

P6

N6

P7

N7

Firing Control

Pulse Pattern (64 bits)

Delay Profile (17 bits)

Finite State

Machine

(FSM)

4-Wire

Serial

Interface

PLL

Voltage Supply to Core

Voltage Supply to I/O

TX_EN

RST

sRD

sWR

sLE

sCLK

REF 40MHz

+1.8V

+3.3V

160 MHz

Fire

Load

LM96570

SNAS505E – AUGUST 2010 – REVISED MAY 2013

www.ti.com

OVERVIEW

The LM96570 beamformer provides an 8-channel transmit side solution for medical ultrasound applications

suitable for integration into multi-channel (128 / 256 channel) systems. Its flexible, integrated pulse pattern

generation and delay architecture enables low-power designs suitable for ultra-portable applications. A complete

system can be designed using Texas Instruments' companion LM9655x chipset.

Figure 7. Block Diagram of Beamformer with Pattern and Delay Generator

A functional block diagram of the IC is shown in Figure 7. Each of the 8 output channels are designed to drive

the positive and negative pulse control inputs, Pn and Nn, respectively, of a high-voltage ultrasound pulser, such

as the LM96550. Upon assertion of the common firing signal, each channel launches an individually

programmable pulse pattern with a maximum delay of 102.4µs in adjustable in increments of 0.78 ns. The length

of a fired pulse pattern can extend up to 64 pulses. Accurate timing of the pulse generation is enabled by an on-

chip PLL generating 8-phase 160 MHz internal clocks derived from an external differential or single-ended

40MHz reference.

The pulse patterns and delay settings can be programmed into and read out from the individual channel controls

via a four-wire serial interface. When the Latch Enable signal (sLE) is low, the targeted on-chip registers can be

written though the serial data Write pin (sWR) at the positive clock edge (sCLK). In the same way, they can also

be read out through the serial data Read pin (sRD). The writing and reading operations have the same timing

requirements, which are shown in Figure 3 and Figure 4. The serial data stream starts with a 6-bit address, in

which the first 5-bits identify the mode of updating which is interpreted by the Finite State Machine (FSM), and

the sixth bit of the address indicates the 4-wire serial operation, either “WRITE” (0) or “READ” (1). The address is

followed by the data word, whose length can vary from 8 bits to 64 bits. The data stream starts with the LSB and

ends with the MSB. The first 5-bit address indicates which of the 27 registers is being accessed. The register

map is shown in Table 3. In each 4-wire serial operation, only one register can be written to or read from at a

time. TX_EN must be inactive during 4-wire serial interface operation.

Upon a rising edge of the transmit signal “TX_EN”, the internal “Fire” signal is pulled high after an internal

propagation delay relative to TX_EN elapses. Then the delay counter of each channel begins counting according

to the programmable delay profile. When the counter reaches the 17-bit programmed delay value, the

programmed pulse pattern is sent out continuously at the programmed frequency until it reaches the length of the

pulse pattern.

8

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