LM96511_15 datasheet(4/74 Pages) TI1

tên linh kiện	LM96511

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LM96511

SNAS476H – MAY 2010 – REVISED MAY 2013

www.ti.com

List of Figures

2-1

Simplified LM96511 Block Diagram

............................................................................................. 8

2-2

8-Channel Transmit/Receive Chipset

........................................................................................... 9

2-3

376–Pin NFBGA Package (18 Rows by 32 Columns)

See Package Number NZJ0376A

.............................................................................................. 10

2-4

376–Pin NFBGA Package (18 Rows by 32 Columns)

See Package Number NZJ0376A

.............................................................................................. 10

4-1

B-Mode ADC Data Output Timing

.............................................................................................. 24

4-2

B-Mode ADC Data Output Level Definitions

.................................................................................. 25

4-3

CW CLK Level Definitions

....................................................................................................... 25

4-4

SPI™ Write Timing

............................................................................................................... 25

4-5

SPI™ Read Timing

............................................................................................................... 26

4-6

CW/DVGA RST Timing (CW Doppler Mode)

................................................................................. 26

6-1

Ultra-Sound System Block Diagram

........................................................................................... 32

6-2

Signal Path (B-Mode) Single Channel

Including Input Clamp and Diode Bridge

...................................................................................... 33

6-3

Standard Input Termination

..................................................................................................... 34

6-4

Active Termination Schematic

.................................................................................................. 35

6-5

Offset Distribution Histogram including Soft-Trim Improvement

........................................................... 35

6-6

LM96511 in Typical TGC Operation at 5MHz

................................................................................ 36

6-7

Periodic TGC Ramp: Example 1 (Half-Step Disable bit = 1)

............................................................... 37

6-8

DVGA UP bit Change (Half-Step Disable bit = 1)

............................................................................ 38

6-9

Periodic TGC Ramp: Example 2 (Half Step Disable bit = 1)

............................................................... 38

6-10

Basic Gain Adjustment (Half Step Disable Bit = 1)

.......................................................................... 39

6-11

Accelerated Gain Adjustment (Half Step Disable bit = 1)

................................................................... 39

6-12

Gain Reset with DVGA UP bit = 0

............................................................................................. 40

6-13

DVGA Gain control “Micro Illustration” of the Gain Stair Case

............................................................. 40

6-14

LM96511 ADC Block Diagram

.................................................................................................. 42

6-15

ADC WCLK

....................................................................................................................... 43

6-16

PLL Phase Noise Transfer Function: ADC CLK = 40 MHz

................................................................. 45

6-17

Digital Filter Transfer Function

................................................................................................. 46

6-18

DAC LPF Capacitor

.............................................................................................................. 47

6-19

LVDS Training Sequence

....................................................................................................... 48

6-20

Reference Sharing

............................................................................................................... 49

6-21

Signal Path (CW Doppler) Single Channel

................................................................................... 50

6-22

I-V with Integrated 2–Pole LFP

................................................................................................. 50

6-23

CW Doppler LPF Gain/Phase Characteristics

................................................................................ 51

6-24

CW Doppler Output (I or Q) Implementation (64 Receive Channels)

..................................................... 53

6-25

CW Doppler Low-Phase Noise Clock Source Design

....................................................................... 54

6-26

LM3881 Power Sequencer Can be Used for Proper LM96511 Power-Up

............................................... 56

6-27

SPI™ Bus Master Slave Connection

.......................................................................................... 56

6-28

SPI™ Compatible Read/Write Timing Diagram

.............................................................................. 57

6-29

SPI™ Compatible Interconnect for Multiple LM96511's (Open Drain Mode)

............................................. 58

6-30

CW Doppler Shadow Register Representation

............................................................................... 67

4

List of Figures

Số phần tương tự - LM96511_15

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Texas Instruments	LM96511CCSMNOPB	6Mb / 66P	[Old version datasheet] Ultrasound Receive Analog Front End (AFE)

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Mô tả tương tự - LM96511_15

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Texas Instruments	LM96511	6Mb / 66P	[Old version datasheet] Ultrasound Receive Analog Front End (AFE)
Texas Instruments	AFE5808A	1Mb / 83P	[Old version datasheet] Ultrasound Analog Front-End
Analog Devices	AD9674	963Kb / 48P	Octal Ultrasound Analog Front End
Texas Instruments	AFE5818	2Mb / 156P	[Old version datasheet] 16-Channel, Ultrasound, Analog Front-End
	AFE5805	417Kb / 32P	[Old version datasheet] 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND
	AFE5807ZCF	1Mb / 74P	[Old version datasheet] Fully Integrated, 8-Channel Ultrasound Analog Front End
	AFE5803	790Kb / 52P	[Old version datasheet] Fully Integrated, 8-Channel Ultrasound Analog Front End
Maxim Integrated Produc...	MAX2077	1Mb / 19P	Octal-Channel Ultrasound Front-End Rev 0; 7/09
	MAX2077	1Mb / 19P	Octal-Channel Ultrasound Front-End 19-4696; Rev 2; 5/19
	MAX2078	1Mb / 26P	Octal-Channel Ultrasound Front-End v 19-4570; Rev 4; 6/19

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