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LM53603AQPWPTQ1 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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LM53603AQPWPTQ1 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 40 page VOUT RESET High = Power Good Low = Fault 94% 93% 107% 106% 11 LM53602-Q1, LM53603-Q1 www.ti.com SNVSA42B – JUNE 2015 – REVISED MAY 2016 Product Folder Links: LM53602-Q1 LM53603-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 RESET Flag Output The RESET function, built-in to the LM53603-Q1, has special features not found in the ordinary power-good function. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line and load transients. Furthermore, there is a delay between the point at which the output voltage is within specified limits and the flag asserts "power-good". Since the RESET comparator and the regulation loop share the same reference, the thresholds will track with the output voltage. This allows the LM53603-Q1 to be specified with a 96.5% maximum threshold, while at the same time specifying a 95% threshold with respect to the actual output voltage for that device. This allows tighter tolerance than is possible with an external supervisor device. The net result is a more accurate power-good function while expanding the system allowance for transients, etc. RESET operation can best be understood by reference to Figure 7 and Figure 8. The values for the various filter and delay times can be found in the Timing Requirements table. Output voltage excursions lasting less than TRESET-filter, will not trip RESET. Once the output voltage is within the prescribed limits, a delay of TRESET-act is imposed before RESET goes high. This output consists of an open drain NMOS; requiring an external pull-up resistor to a suitable logic supply. It can also be pulled-up to either VCC or VOUT, through an appropriate resistor, as desired. If this function is not needed, the pin should be left floating or grounded. When EN is pulled low, the flag output will also be forced low. With EN low, RESET will remain valid as long as the input voltage is ≥ 1.5 V. The maximum current into this pin should be limited to 1 mA, while the maximum voltage should be less than 8 V. Figure 7. Static RESET Operation |
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