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74ALVCH162841DLG4 bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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74ALVCH162841DLG4 bảng dữ liệu(HTML) 9 Page - Texas Instruments |
9 / 15 page www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 6 V Open GND 500 Ω 500 Ω tPLH tPHL Output Control (low-level enabling) Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 1.5 V 1.5 V 1.5 V 1.5 V 2.7 V 0 V 1.5 V 1.5 V VOH VOL 0 V 1.5 V VOL + 0.3 V 1.5 V VOH − 0.3 V 0 V 1.5 V 2.7 V 0 V 1.5 V 1.5 V 0 V 2.7 V 0 V 1.5 V 1.5 V tw Input 2.7 V 2.7 V 3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Output Input tpd tPLZ/tPZL tPHZ/tPZH Open 6 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, trv2.5 ns, tfv2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 V CC = 2.7 V AND 3.3 V ± 0.3 V Figure 3. Load Circuit and Voltage Waveforms 9 |
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