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SN74ACT3622-15PQG4 bảng dữ liệu(PDF) 11 Page - Texas Instruments

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SN74ACT3622-15PQG4 bảng dữ liệu(HTML) 11 Page - Texas Instruments

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SN74ACT3622
256
× 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247D – AUGUST 1993 – REVISED APRIL 1998
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA and with MBA high. A low-to-high transition on CLKB
writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB
high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail
register are ignored while the mail flag is low.
When data outputs of a port are active, the data on the bus comes from the FIFO output register when the
port-mailbox-select input is low and from the mail register when the port-mailbox-select input is high. The mail1
register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB,
W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on
CLKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register
remains intact after it is read and changes only when new data is written to the register.
CLKA
CLKB
RST1
0,1
th(FS)
tsu(FS)
th(RS)
tsu(RS)
FS1, FS0
IRA
tpd(C-IR)
tpd(C-IR)
ORB
tpd(C-OR)
tpd(R-F)
tpd(R-F)
AEB
AFA
MBF1
tpd(R-F)
Figure 1. FIFO1 Reset Loading X1 and Y1 With a Preset Value of Eight
† FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.


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