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SN74ACT533DBLE bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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SN74ACT533DBLE bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 10 page SN54ACT533, SN74ACT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCAS553C – NOVEMBER 1995 – REVISED OCTOBER 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 11 ns at 5 V D Inputs Are TTL-Voltage Compatible D 3-State Inverting Outputs Drive Bus Lines Directly description/ordering information The ’ACT533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverted levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74ACT533N SN74ACT533N SOIC DW Tube SN74ACT533DW ACT533 40 °Cto85°C SOIC – DW Tape and reel SN74ACT533DWR ACT533 –40 °C to 85°C SOP – NS Tape and reel SN74ACT533NSR ACT533 SSOP – DB Tape and reel SN74ACT533DBR AD533 TSSOP – PW Tape and reel SN74ACT533PWR AD533 CDIP – J Tube SNJ54ACT533J SNJ54ACT533J –55 °C to 125°C CFP – W Tube SNJ54ACT533W SNJ54ACT533W LCCC – FK Tube SNJ54ACT533K SNJ54ACT533FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE SN54ACT533 ...J OR W PACKAGE SN74ACT533 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 32 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 8D 7D 7Q 6Q 6D 2D 2Q 3Q 3D 4D SN54ACT533 . . . FK PACKAGE (TOP VIEW) |
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