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SN74ABT657ADWRE4 bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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1 / 13 page SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D Flow-Through Architecture Optimizes PCB Layout D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description Th e'ABT657A transceivers have eight noninverting buffers with parity-generator/ checker circuits and control signals. The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state. Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode. In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high. In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is low, indicating a parity error. Copyright © 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC- ΙΙB is a trademark of Texas Instruments Incorporated. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY SN54ABT657A . . . JT PACKAGE SN74ABT657A . . . DW OR NT PACKAGE (TOP VIEW) 32 1 28 27 12 13 5 6 7 8 9 10 11 25 24 23 22 21 20 19 A3 A2 A1 NC T/R OE B1 ODD/EVEN ERR PARITY NC B8 B7 B6 4 26 14 15 16 17 18 SN54ABT657A . . . FK PACKAGE (TOP VIEW) NC – No internal connection |
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