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SN74ABT3611-20PCB bảng dữ liệu(PDF) 10 Page - Texas Instruments

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SN74ABT3611
64
× 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
parity checking (continued)
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more bytes of a port is reported by a low level on the corresponding port parity
error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, and
port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35. When odd/even parity is selected,
PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to its bits.
The four parity trees used to check the A0 – A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, PEFA is held high, regardless of the
levels applied to the A0 – A35 inputs. Likewise, the parity trees used to check the B0 – B35 inputs are shared
by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from
the mail1 register with parity generation is selected with CSB low, ENB high, W/RB low, MBB high, and PGB
high, PEFB is held high, regardless of the levels applied to the B0 – B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN74ABT3611 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit.
Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs, regardless
of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the
ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the
most-significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. Therefore, the port-B parity generate select (PGB) and ODD/EVEN have setup- and hold-time
constraints to the port-B clock (CLKB) for a rising edge of CLKB used to read a new word to the FIFO output
register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0 – B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0 – A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when W/RA, W/RB
is low, MBA, MBB is high, CSA, CSB is low, ENA, ENB is high, and PGA, PGB is high. Generating parity for
mail-register data does not change the contents of the register.


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