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SN74ABT3612 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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SN74ABT3612 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 34 page SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 parity generation (continued) Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port-A parity generate select (PGA) and odd/even parity select (ODD/EVEN) have setup- and hold-time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB) and ODD/EVEN have setup- and hold-time constraints to the port-B clock (CLKB). These timing constraints apply only for a rising clock edge used to read a new word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0 – B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0 – A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when W/RA, W/RB is low; MBA, MBB is high; CSA, CSB is low; ENA, ENB is high; and PGA, PGB is high. Generating parity for mail-register data does not change the contents of the register. tpd(C-AF) CLKA CLKB RST 0,1 th(FS) tsu(FS) th(RS) tsu(RS) FS1, FS0 FFA tpd(C-FF) tpd(C-FF) EFA tpd(C-EF) tpd(C-AE) AEA AFA MBF1, MBF2 tpd(R-F) tpd(C-FF) tpd(C-FF) FFB EFB tpd(C-AF) tpd(C-AE) AEB AFB tpd(C-EF) Figure 1. Device Reset Loading the X Register With the Value of Eight |
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Mô tả tương tự - SN74ABT3612 |
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