A1

B1

C1

D1

A3

B3

C3

D3

SGND

A2

D2

EN

BYPOUT

SW

PGND

FB

BYP

A3

B3

C3

D3

A1

B1

C1

D1

SGND

A2

D2

EN

BYPOUT

SW

PGND

FB

BYP

LM3204

SNVS351C – JUNE 2005 – REVISED APRIL 2013

www.ti.com

CONNECTION DIAGRAMS

Figure 1. Top View

Figure 2. Bottom View

10–Bump Thin DSBGA Package, Large Bump.

See NS Package Number YPA0010NHA.

PIN DESCRIPTION

Pin #

Name

Description

A1

Analog Supply Input. A 0.1µF ceramic capacitor is recommended to be placed as close to this pin as possible.

(Figure 34)

B1

C1

FB

Feedback Analog Input. Connect to the output at the output filter capacitor. (Figure 34)

D1

BYP

Bypass. Use this digital input to command operation in Bypass mode. Set BYP low (<0.4V) for normal

operation.

D2

EN

Enable Input. Set this digital input high (>1.2V) after Vin >2.7V for normal operation. For shutdown, set low

(<0.4V).

D3

PGND

Power Ground

C3

SW

Switching Node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit

specification of the LM3204.

B3

Power Supply Voltage Input to the internal PFET switch and Bypass FET. (Figure 34)

A3

BYPOUT

Bypass FET Drain. Connect to the output capacitor. (Figure 34) Do not leave floating.

A2

SGND

Analog and Control Ground

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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