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LM2642MTCX bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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LM2642MTCX bảng dữ liệu(HTML) 2 Page - Texas Instruments |
2 / 31 page RSNS1 SW1 HDRV1 CBOOT1 VDD1 LDRV1 VIN PGND LDRV2 VDD2 CBOOT2 HDRV2 SW2 RSNS2 KS2 ILIM2 COMP2 FB2 ON/SS2 ON/SS1 SGND VLIN5 UVDELAY PGOOD1 FB1 COMP1 ILIM1 KS1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM TOP VIEW Figure 1. 28-Lead TSSOP PIN DESCRIPTIONS KS1 (Pin 1) The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to connect this pin to the current sense point. It should be connected to VIN as close as possible to the node of the current sense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the upper MOSFET. ILIM1 (Pin 2) Current limit threshold setting for Channel 1. It sinks a constant current of 10 µA, which is converted to a voltage across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the VDS of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current condition has occurred in Channel 1. COMP1 (Pin 3) Compensation pin for Channel 1. This is the output of the internal transconductance amplifier. The compensation network should be connected between this pin and the signal ground, SGND (Pin 8). FB1 (Pin 4) Feedback input for channel 1. Connect to VOUT through a voltage divider to set the channel 1 output voltage. PGOOD1 (Pin 5) An open-drain power-good output for Channel 1. It is 'LOW' (low impedance to ground) whenever the output voltage of Channel 1 falls outside of a +15% to -9% window. PGOOD1 stays latched in a 'LOW' state during OVP or UVP on either channel. It will recover to a 'HIGH' state (high impedance to ground) after a Channel 1 output under-voltage event (<91%) when the output returns to within 6% of its nominal value. See Operation Descriptions for details. UV_DELAY (Pin 6) A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5µA current source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to ground will disable the output under-voltage protection. VLIN5 (Pin 7) The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and supplies the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7µF capacitor. SGND (Pin 8) The ground connection for the signal-level circuitry. It should be connected to the ground rail of the 2 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM2642 |
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