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SM320F28335KGDS1 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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SM320F28335KGDS1 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 182 page  SM320F28335-HT SPRS682E – DECEMBER 2010 – REVISED JANUARY 2014 www.ti.com 6-6 XCLKIN Timing Requirements - PLL Enabled ............................................................................. 122 6-7 XCLKIN Timing Requirements - PLL Disabled ............................................................................. 122 6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 122 6-9 Power Management and Supervisory Circuit Solutions ................................................................... 123 6-10 Reset (XRS) Timing Requirements .......................................................................................... 125 6-11 General-Purpose Output Switching Characteristics ........................................................................ 126 6-12 General-Purpose Input Timing Requirements .............................................................................. 127 6-13 IDLE Mode Timing Requirements ........................................................................................... 129 6-14 IDLE Mode Switching Characteristics ....................................................................................... 129 6-15 STANDBY Mode Timing Requirements ..................................................................................... 129 6-16 STANDBY Mode Switching Characteristics ................................................................................ 130 6-17 HALT Mode Timing Requirements ........................................................................................... 131 6-18 HALT Mode Switching Characteristics ...................................................................................... 131 6-19 ePWM Timing Requirements ................................................................................................. 133 6-20 ePWM Switching Characteristics ............................................................................................ 133 6-21 Trip-Zone input Timing Requirements ....................................................................................... 133 6-22 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 120 MHz) .............................................. 134 6-23 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 134 6-24 eCAP Switching Characteristics ............................................................................................. 134 6-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 134 6-26 eQEP Switching Characteristics ............................................................................................. 134 6-27 External ADC Start-of-Conversion Switching Characteristics ............................................................. 135 6-28 External Interrupt Timing Requirements .................................................................................... 135 6-29 External Interrupt Switching Characteristics ................................................................................ 135 6-30 I2C Timing ...................................................................................................................... 136 6-31 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 137 6-32 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 139 6-33 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 140 6-34 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 142 6-35 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 143 6-36 XINTF Clock Configurations ................................................................................................... 146 6-37 External Interface Read Timing Requirements ............................................................................. 147 6-38 External Interface Read Switching Characteristics ......................................................................... 147 6-39 External Interface Write Switching Characteristics ......................................................................... 148 6-40 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ................................... 150 6-41 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 150 6-42 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 150 6-43 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 150 6-44 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 153 6-45 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 153 6-46 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 153 6-47 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 156 6-48 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 157 6-49 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 159 6-50 ADC Power-Up Delays ......................................................................................................... 160 6-51 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 160 6-52 Sequential Sampling Mode Timing ........................................................................................... 162 6-53 Simultaneous Sampling Mode Timing ....................................................................................... 163 8 List of Tables Copyright © 2010–2014, Texas Instruments Incorporated |
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