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SM320F28335GBS bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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SM320F28335GBS bảng dữ liệu(HTML) 2 Page - Texas Instruments |
2 / 182 page SM320F28335-HT www.ti.com SPRS682E – DECEMBER 2010 – REVISED JANUARY 2014 Contents 1 SM320F28335 DSC ............................................................................................................. 10 1.1 Features .................................................................................................................... 10 1.2 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 11 1.3 ORDERING INFORMATION ............................................................................................. 11 2 Introduction ...................................................................................................................... 12 2.1 Pin Assignments ........................................................................................................... 13 2.2 Die Layout .................................................................................................................. 19 2.3 Signal Descriptions ........................................................................................................ 26 3 Functional Overview .......................................................................................................... 42 3.1 Memory Maps .............................................................................................................. 43 3.2 Brief Descriptions .......................................................................................................... 47 3.2.1 C28x CPU ....................................................................................................... 47 3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 47 3.2.3 Peripheral Bus .................................................................................................. 47 3.2.4 Real-Time JTAG and Analysis ................................................................................ 48 3.2.5 External Interface (XINTF) .................................................................................... 48 3.2.6 Flash ............................................................................................................. 48 3.2.7 M0, M1 SARAMs ............................................................................................... 48 3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 48 3.2.9 Boot ROM ....................................................................................................... 49 3.2.10 Security .......................................................................................................... 49 3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 50 3.2.12 External Interrupts (XINT1-XINT7, XNMI) ................................................................... 51 3.2.13 Oscillator and PLL .............................................................................................. 51 3.2.14 Watchdog ........................................................................................................ 51 3.2.15 Peripheral Clocking ............................................................................................. 51 3.2.16 Low-Power Modes .............................................................................................. 51 3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 52 3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 52 3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 52 3.2.20 Control Peripherals ............................................................................................. 53 3.2.21 Serial Port Peripherals ......................................................................................... 53 3.3 Register Map ............................................................................................................... 54 3.4 Device Emulation Registers .............................................................................................. 55 3.5 Interrupts .................................................................................................................... 56 3.5.1 External Interrupts .............................................................................................. 60 3.6 System Control ............................................................................................................ 60 3.6.1 OSC and PLL Block ............................................................................................ 62 3.6.1.1 External Reference Oscillator Clock Option .................................................... 63 3.6.1.2 PLL-Based Clock Module ......................................................................... 63 3.6.1.3 Loss of Input Clock ................................................................................ 65 3.6.2 Watchdog Block ................................................................................................. 65 3.7 Low-Power Modes Block ................................................................................................. 66 4 Peripherals ....................................................................................................................... 67 4.1 DMA Overview ............................................................................................................. 67 4.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 69 4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) ......................................................................... 71 4.4 High-Resolution PWM (HRPWM) ....................................................................................... 75 4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ........................................................................... 75 4.6 Enhanced QEP Modules (eQEP1/2) .................................................................................... 78 4.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 80 2 Contents Copyright © 2010–2014, Texas Instruments Incorporated |
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