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SM320C6727B bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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SM320C6727B bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 111 page  SM320C6727B www.ti.com SPRS861 – JANUARY 2014 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the C6727B DSPs. The table shows significant features of each device, including the capacity of on-chip memory, the peripherals, the execution time, and the package type with pin count. Table 2-1. Characteristics of the C6727B Processors HARDWARE FEATURES dMAX 1 EMIF 1 (32-bit) Peripherals UHPI 1 Not all peripheral pins are available at the same McASP 3 time. (For more details, see the Device SPI 2 Configurations section.) I2C 2 RTI 1 32KB Program Cache On-Chip Memory Size (KB) 256KB RAM 384KB ROM Control Status Register CPU ID + CPU Rev ID 0x0300 (CSR.[31:16]) Frequency MHz 250 Cycle Time ns 4 ns EMIF Frequency MHz 133 1.4 V (C6727B-350) 1.2 V Core (V) (C6727B-300) Voltage (C6727B-275) (C6727BA-250) I/O (V) 3.3 V Prescaler /1, /2, /3, ..., /32 Clock Generator Options Multiplier x4, x5, x6, ..., x25 Postscaler /1, /2, /3, ..., /32 Package (see Section 6) 36 x 36 mm 256-Pin CQFP (HFH) Process Technology µm 0.13 µm Product Preview (PP), Product Status Advance Information (AI), or PD(1) Production Data (PD) (1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.2 Enhanced C67x+ CPU The SM320C6727B floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant enhancements including an increase in core operating frequency of 250 MHz while operating at 1.2 V. The CPU fetches 256-bit-wide advanced very-long instruction word (VLIW) fetch packets that are composed of variable-length execute packets. The execute packets can supply from one to eight 32-bit instructions to the eight functional units during every clock cycle. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. Additionally, execute packets can now span fetch packets, providing a code size improvement over the C67x CPU core. Copyright © 2014, Texas Instruments Incorporated Device Overview 7 Submit Documentation Feedback Product Folder Links: SM320C6727B |
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