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LM2574HVMX-12/NOPB bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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LM2574HVMX-12/NOPB bảng dữ liệu(HTML) 3 Page - Texas Instruments |
3 / 38 page 1 NC 14 NC 2 NC 13 NC 3 FB 12 OUTPUT 4 SIG_GND 11 NC 5 ON/OFF 10 V IN 6 PWR_GND 9 NC 7 NC 8 NC 1 FB 8 NC 2 SIG_GND 7 OUTPUT 3 ON/OFF 6 NC 4 PWR_GND 5 V IN 3 LM2574, LM2574HV www.ti.com SNVS104D – JUNE 1999 – REVISED APRIL 2016 Product Folder Links: LM2574 LM2574HV Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions P Package 8-Pin PDIP Top View NPA Package 14-Pin SOIC Top View Pin Functions PIN I/O DESCRIPTION NAME PDIP SOIC FB 1 3 I Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT for ADJ version or connect this pin directly to the output capacitor for a fixed output version. NC 8, 6 1, 2, 7, 8, 9, 11, 13, 14 — No internal connection, but must be soldered to PCB for best heat transfer. ON/OFF 3 5 I Enable input to the voltage regulator. High = OFF and low = ON. Connect to GND to enable the voltage regulator. Do not leave this pin float. OUTPUT 7 12 O Emitter pin of the power transistor. This is a switching node. Attached this pin to an inductor and the cathode of the external diode. PWR_GND 4 6 — Power ground pins. Connect to system ground and SIF GND, ground pins of CIN and COUT. Path to CIN must be as short as possible. SIG_GND 2 4 — Signal ground pin. Ground reference for internal references and logic. Connect to system ground. VIN 5 10 I Supply input pin to collector pin of high-side transistor. Connect to power supply and input bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PWR GND must be as short as possible. |
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