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LM118-N, LM218-N, LM318-N
SNOSBS8C – MARCH 1998 – REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage
±20V
Power Dissipation (3)
500 mW
Differential Input Current (4)
±10 mA
Input Voltage (5)
±15V
Output Short-Circuit Duration
Continuous
Operating Temperature Range
lm118-n
−55°C to +125°C
LM218-N
−25°C to +85°C
LM318-N
0°C to +70°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature (Soldering, 10 sec.)
TO-99 Package
300°C
PDIP Package
260°C
Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
260°C
SOIC Package
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
ESD Tolerance (6)
2000V
(1)
Refer to RETS118X for LM118H and LM118J military specifications.
(2)
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3)
The maximum junction temperature of the lm118-n is 150°C, the LM218-N is 110°C, and the LM318-N is 110°C. For operating at
elevated temperatures, devices in the LMC package must be derated based on a thermal resistance of 160°C/W, junction to ambient, or
20°C/W, junction to case. The thermal resistance of the dual-in-line package is 100°C/W, junction to ambient.
(4)
The inputs are shunted with back-to-back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1V is applied between the inputs unless some limiting resistance is used.
(5)
For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
(6)
Human body model, 1.5 k
Ω in series with 100 pF.
Electrical Characteristics
(1)
Parameter
Conditions
LM118-N/LM218-N
LM318-N
Units
Min
Typ
Max
Min
Typ
Max
Input Offset Voltage
TA = 25°C
2
4
4
10
mV
Input Offset Current
TA = 25°C
6
50
30
200
nA
Input Bias Current
TA = 25°C
120
250
150
500
nA
Input Resistance
TA = 25°C
1
3
0.5
3
M
Ω
Supply Current
TA = 25°C
5
8
5
10
mA
Large Signal Voltage Gain
TA = 25°C, VS = ±15V
50
200
25
200
V/mV
VOUT = ±10V, RL ≥ 2 kΩ
Slew Rate
TA = 25°C, VS = ±15V, AV = 1
50
70
50
70
V/
μs
(2)
Small Signal Bandwidth
TA = 25°C, VS = ±15V
15
15
MHz
Input Offset Voltage
6
15
mV
Input Offset Current
100
300
nA
(1)
These specifications apply for ±5V
≤ VS ≤ ±20V and −55°C ≤ TA ≤ +125°C (lm118-n), −25°C ≤ TA ≤ +85°C (LM218-N), and 0°C ≤ TA
+70°C (LM318-N). Also, power supplies must be bypassed with 0.1
μF disc capacitors.
(2)
Slew rate is tested with VS = ±15V. The lm118-n is in a unity-gain non-inverting configuration. VIN is stepped from −7.5V to +7.5V and
vice versa. The slew rates between
−5.0V and +5.0V and vice versa are tested and specified to exceed 50V/μs.
2
Submit Documentation Feedback
Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: LM118-N LM218-N LM318-N


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