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LM1973 bảng dữ liệu(PDF) 10 Page - Texas Instruments

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LM1973
SNAS093B – DECEMBER 1994 – REVISED MARCH 2013
www.ti.com
Table 1. LM1973 Micropot Attenuator
Register Set Description (continued)
MSB:
LSB
Address Register (Byte 0)
: : : : :
: :
0011 1110
46.0
0011 1111
47.0
0100 0000
48.0
0100 0001
50.0
0100 0010
52.0
: : : : :
: :
0100 1100
72.0
0100 1101
74.0
0100 1110
76.0
0100 1111
100.0 (Mute)
0101 0000
100.0 (Mute)
: : : : :
: :
1111 1110
100.0 (Mute)
1111 1111
100.0 (Mute)
μPot SYSTEM ARCHITECTURE
The
μPot's digital interface is essentially a shift register, where serial data is shifted in, latched, and then
decoded. As new data is shifted into the DATA-IN pin, the previously latched data is shifted out the DATA-OUT
pin. Once the data is shifted in, the LOAD/SHIFT line goes high, latching in the new data. The data is then
decoded and the appropriate switch is activated to set the desired attenuation level for the selected channel. This
process is continued each and every time an attenuation change is made. Each channel is updated, only, when
that channel is selected for an attenuator change or the system is powered down and then back up again. When
the
μPot is powered up, each channel is placed into the muted mode.
μPot LADDER ARCHITECTURE
Each channel of a
μPot has its own independent resistor ladder network. As shown in Figure 21, the ladder
consists of multiple R1/R2 elements which make up the attenuation scheme. Within each element there are tap
switches that select the appropriate attenuation level corresponding to the data bits in Table 1. It can be seen in
Figure 21 that the input impedance for the channel is a constant value regardless of which tap switch is selected,
while the output impedance varies according to the tap switch selected.
Figure 21.
μPot Ladder Architecture
DIGITAL LINE COMPATIBILITY
The
μPot's digital interface section is compatible with either TTL or CMOS logic due to the shift register inputs
acting upon a threshold voltage of 2 diode drops or approximately 1.4V.
10
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