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DAC101S101CIMM bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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DAC101S101CIMM bảng dữ liệu(HTML) 3 Page - Texas Instruments |
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3 / 37 page  1 V 8 GND 2 NC 7 D 3 NC 6 SCLK 4 V 5 SYNC A IN OUT 1 V 6 SYNC 2 GND 5 SCLK 3 V 4 D OUT IN A 3 DAC101S101, DAC101S101-Q1 www.ti.com SNAS321G – JUNE 2005 – REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated 5 Description (continued) The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in battery operated equipment. The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended industrial temperature range of −40°C to +105°C while the DAC101S101Q operates over the Grade 1 automotive temperature range of −40°C to +125°C. The DAC101S101 is available in a 6-lead SOT and an 8-lead VSSOP and the DAC101S101Q is availabe in the 6-lead SOT only. 6 Pin Configuration and Functions DAC101S101 and DAC101S101-Q1 DDC Package 6-Pin (SOT-23) Top View DAC101S101 DGK Package 8-Pin (VSSOP) Top View (1) G = Ground, I = Input, O = Output, S = Supply Pin Functions PIN I/O(1) DESCRIPTION NAME DAC101S101 DAC101S101-Q1 SOT-23 VSSOP SOT-23 DIN 4 7 4 I Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. GND 2 8 2 G Ground reference for all on-chip circuitry. NC – 2,3 – – No Connect. There is no internal connection to these pins. SCLK 5 6 5 I Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. SYNC 6 5 6 I Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. VA 3 1 3 S Power supply and Reference input. Should be decoupled to GND. VOUT 1 4 1 O DAC Analog Output Voltage. |
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