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DAC082S085 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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DAC082S085 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 31 page  Not to scale 1 VA 10 SCLK 2 VOUTA 9 SYNC 3 VOUTB 8 DIN 4 NC 7 VREFIN 5 NC 6 GND Not to scale Exposed Thermal Pad 1 VA 10 SCLK 2 VOUTA 9 SYNC 3 VOUTB 8 DIN 4 NC 7 VREFIN 5 NC 6 GND 4 DAC082S085 SNAS365G – MAY 2006 – REVISED JUNE 2016 www.ti.com Product Folder Links: DAC082S085 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 6 Pin Configuration and Functions DSC Package 10-Pin WSON Top View DGS Package 10-Pin VSSOP Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 VA Supply Power supply input. Must be decoupled to GND. 2 VOUTA Analog Output Channel A analog output voltage. 3 VOUTB Analog Output Channel B analog output voltage. 4 NC — Not connected 5 NC — Not connected 6 GND Ground Ground reference for all on-chip circuitry. 7 VREFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled to GND. 8 DIN Digital Input Serial data input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. 9 SYNC Digital Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 10 SCLK Digital Input Serial clock input. Data is clocked into the input shift register on the falling edges of this pin. PAD PAD Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. |
Số phần tương tự - DAC082S085 |
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Mô tả tương tự - DAC082S085 |
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