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CD4053B-Q1-MIL bảng dữ liệu(PDF) 1 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Features
D Qualified for Automotive Applications
D Wide Range of Digital and Analog Signal
Levels
− Digital: 3 V to 20 V
− Analog:
3 20 VP-P
D Low ON Resistance, 125 Ω (Typ) Over
15 VP-P Signal Input Range
for VDD − VEE = 18 V
D High OFF Resistance, Channel Leakage of
+100 pA (Typ) at VDD − VEE = 18 V
D Logic-Level Conversion for Digital
Addressing Signals of 3 V to 20 V
(VDD − VSS = 3 V to 20 V) to Switch Analog
Signals to 20 VP-P (VDD − VEE = 20 V)
D Matched Switching Characteristics,
ron = 5 Ω (Typ) for VDD − VEE = 15 V
D Very Low Quiescent Power Dissipation
Under All Digital-Control Input and Supply
Conditions, 0.2
µW (Typ)
at VDD − VSS = VDD − VEE = 10 V
D Binary Address Decoding on Chip
D 5-V, 10-V, and 15-V Parametric Ratings
D 100% Tested for Quiescent Current at 20 V
D Maximum Input Current of 1µA at 18 V Over
Full Package Temperature Range, 100 nA at
18 V and 25
°C
D Break-Before-Make Switching Eliminates
Channel Overlap
Applications
D Analog and Digital Multiplexing and
Demultiplexing
D Analog-to-Digital (A/D) and
Digital-to-Analog (D/A) Conversion
D Signal Gating
description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have
low ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved
by digital signal amplitudes of 4.5 V to 20 V (If VDD − VSS = 3 V, a VDD − VEE of up to 13 V can be controlled;
for VDD − VEE level differences above 13 V, a VDD − VSS of at least 4.5 V is required). For example, if
VDD = 4.5 V, VSS = 0 V, and VEE = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital
inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD − VSS
and VDD − VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic high
(H) is present at the inhibit (INH) input, all channels are off.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − M
Reel of 2500
CD4051BQM96Q1
CD4051Q
TSSOP − PW
Reel of 2000
CD4051BQPWRQ1
CM051BQ
40
°C to 125°C
SOIC − M
Reel of 2500
CD4052BQM96Q1§
CD4052Q
−40
°C to 125°C
TSSOP − PW
Reel of 2000
CD4052BQPWRQ1§
CD4052Q
SOIC − M
Reel of 2500
CD4053BQM96Q1
CD4053Q
TSSOP − PW
Reel of 2000
CD4053BQPWRQ1§
CD4053Q
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ Product Preview
Copyright
 2008, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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