công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADS8506IDWG4 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
|
ADS8506IDWG4 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 35 page www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS8506 +5 V + + Convert Pulse 40 ns Min 200 Ω 0.1 µF 10 µF 100 Ω + 2.2 µF 66.5 k Ω +5 V Parallel Output B7 B8 B9 B10 B11 (MSB) Pin 21 LOW B1 B2 B3 Pin 21 HIGH NC(1) B4 B5 B6 B0 (LSB) B2 BUSY R/C BYTE ± 10 V 2.2 µF SERIAL OUTPUT ADS8506 SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007 LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight most significant bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the four least significant bits (LSBs) will be valid when BUSY rises. Data will be output in binary 2's complement (BTC) format. BUSY going HIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining byte to be read. All convert commands will be ignored while BUSY is LOW. The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). Figure 31. Basic ±10-V Operation, Both Parallel and Serial Output Figure 32 shows a basic circuit to operate the ADS8506 with a ±10-V input range and serial output. Taking R/C (pin 22) LOW for 40 ns (12 µs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 19) synchronized to 12 clock pulses output on DATACLK (pin 18). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in BTC format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the Calibration section). Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS8506 |
Số phần tương tự - ADS8506IDWG4 |
|
Mô tả tương tự - ADS8506IDWG4 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |