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ADS8329IPWG4 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS8329IPWG4 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 50 page TIMING CHARACTERISTICS ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com All specifications typical at –40°C to 85°C and +VA = +VBD = 5 V. (1) (2) PARAMETER MIN TYP MAX UNIT External, 0.5 21 fCCLK = 1/2 fSCLK fCCLK Frequency, conversion clock, CCLK MHz Internal, 21 22.9 24.5 fCCLK = 1/2 fSCLK tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns Setup time, falling edge of CS to first falling tsu(CSF-SCLK1F) 5 ns SCLK twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) – 8 ns twH(SCLK) Pulse duration, SCLK high 8 tc(SCLK) – 8 ns I/O Clock only 20 I/O and conversion clock 23.8 2000 tc(SCLK) Cycle time, SCLK ns I/O Clock, chain mode 20 I/O and conversion clock, 23.8 2000 chain mode Delay time, falling edge of SCLK to SDO td(SCLKF-SDOINVALID) 10-pF Load 2 ns invalid Delay time, falling edge of SCLK to SDO td(SCLKF-SDOVALID) 10-pF Load 10 ns valid Delay time, falling edge of CS to SDO td(CSF-SDOVALID) 10-pF Load 8.5 ns valid, SDO MSB output tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO td(CSR-SDOZ) 5 ns 3-state Setup time, 16th falling edge of SCLK tsu(16th SCLKF-CSR) 10 ns before rising edge of CS/FS Delay time, CDI high to SDO high in daisy td(SDO-CDI) 10-pF Load, chain mode 16 ns chain mode (1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. 8 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 |
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