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ADS8321EB/2K5 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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ADS8321EB/2K5 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 19 page ADS8321 11 SBAS123B www.ti.com Figure 8 shows the current consumption of the ADS8321 versus sample rate. For this graph, the converter is clocked at 2.4MHz regardless of the sample rate—CS is HIGH for the remaining sample period. Figure 9 also shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/24th of the sample period—CS is HIGH for one DCLOCK cycle out of every 16. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode which is enabled when CS is HIGH. CS LOW will shut down only the analog section. The digital section is completely shutdown only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. See Figure 10 for more information. SHORT CYCLING Another way of saving power is to utilize the CS signal to short cycle the conversion. Because the ADS8321 places the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS HIGH) after the 14th bit has been clocked out. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some con- dition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system, as they spend more time in the power-down mode. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8321 circuitry. This will be particularly true if the reference voltage is low and/or the conversion rate is high. At a 100kHz conversion rate, the ADS8321 makes a bit decision every 416ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such spikes might origi- nate from switching power supplies, digital logic, and high FIGURE 8. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Linearly with Sample Rate. FIGURE 9. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate. FIGURE 10. Shutdown Current with CS HIGH is 50nA Typically, Regardless of the Clock. Shutdown Current with CS LOW Varies with Sample Rate. 1000 100 10 1 0.1 1 10 100 Sample Rate (kHz) T A = 25°C V CC = 5.0V V REF = 2.5V f CLK = 2.4MHz 1000 100 10 1 0.1 1 10 100 Sample Rate (kHz) T A = 25°C V CC = 5.0V V REF = 2.5V f CLK = 24 • fSAMPLE 1000 800 600 400 200 0.250 0.00 0.1 1 10 100 Sample Rate (kHz) T A = 25°C V CC = 5.0V V REF = 2.5V f CLK = 24 • fSAMPLE CS LOW (GND) CS HIGH (V CC) |
Số phần tương tự - ADS8321EB/2K5 |
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Mô tả tương tự - ADS8321EB/2K5 |
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