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DM74LS502N bảng dữ liệu(PDF) 3 Page - National Semiconductor (TI) |
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DM74LS502N bảng dữ liệu(HTML) 3 Page - National Semiconductor (TI) |
3 / 6 page Switching Characteristics VCC ea50V TA ea25 C Symbol Parameter DM54LS502 DM74LS502 Units RL e 2kX CL e 15 pF Min Max Min Max fmax Maximum Clock Frequency 25 15 MHz tPLH Propagation Delay 35 35 ns tPHL CP to Qn or CC 25 25 Functional Description The register stages are composed of transparent RS latch- es arranged in masterslave pairs The master and slave latches are enabled separately by non-overlapping comple- mentary signals w1 and w2 derived internally from the CP input Master latches are enabled when CP is LOW and slave latches are enabled when CP is HIGH Information is transferred from master to slave and thus to the outputs by the LOW-to-HIGH transition of CP Initializing the register requires a LOW signal on S while exercising CP With S and CP LOW all master latches are SET (Q side HIGH) A LOW-to-HIGH CP transition with S remaining LOW then forces the slave latches to the condi- tion wherein Q7 is LOW and all other register outputs in- cluding CC are HIGH This condition will prevail as long as S remains LOW regardless of subsequent CP rising edge To start the conversion process S must return to the HIGH state On the next CP rising edge the information stored in the serial data input latch is transferred to QD and Q7 while Q6 is forced to the LOW state On the rising edge of the next seven clocks this LOW signal is shifted downstream one bit at a time while the serial data enters the register position one bit behind this LOW signal as shown in the Truth Table Note that after a serial data bit appears at a particular output that register position undergoes no further changes After the shifted LOW signal reaches CC the reg- ister is locked up and no further changes can occur until the register is initialized for the next conversion process Figure a shows a simplified hook-up of a LS502 a DA con- verter and a comparator arranged to convert an analog in- put voltage into an 8-bit binary number by the successive approximation technique Figure b is an idealized graph showing the various values that the DA converter output voltage can assume in the course of the conversion The vertical axis is calibrated in fractions of the full-scale output capability of the DA converter and the horizontal axis rep- resents the successive states of the Truth Table At time t1 Q7 is LOW and Q6 – Q0 are HIGH causing the DA output to be one-half of full scale If the analog input voltage is greater than this voltage the comparator output (hence the D input of the LS502) will be LOW and at times t2 the DA output will rise to three-fourths of full scale because Q7 will remain LOW and contribute 50% while Q6 is forced LOW and contributes another 25% On the other hand if the ana- log input voltage is less than one-half of full scale the com- parator output will be HIGH and Q7 will go HIGH at t2 Q6 will still be forced LOW at t2 and the DA output will de- crease to 25% of full scale Thus with each successive clock the DA output will change by smaller increments When the conversion is completed at t9 the binary number represented by the register outputs will be the numerator of the fraction n256 representing the analog input voltage as a fraction of the full scale output DA converter TLF10189 – 4 FIGURE a TLF10189 – 5 FIGURE b 3 |
Số phần tương tự - DM74LS502N |
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Mô tả tương tự - DM74LS502N |
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