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ADS7828E bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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ADS7828E bảng dữ liệu(HTML) 5 Page - Texas Instruments |
5 / 22 page ADS7828 5 SBAS181C www.ti.com PARAMETER SYMBOL CONDITIONS MIN MAX UNITS SCL Clock Frequency fSCL Standard Mode 100 kHz Fast Mode 400 kHz High-Speed Mode, CB = 100pF max 3.4 MHz High-Speed Mode, CB = 400pF max 1.7 MHz Bus Free Time Between a STOP and tBUF Standard Mode 4.7 µs START Condition Fast Mode 1.3 µs Hold Time (Repeated) START tHD;STA Standard Mode 4.0 µs Condition Fast Mode 600 ns High-Speed Mode 160 ns LOW Period of the SCL Clock tLOW Standard Mode 4.7 µs Fast Mode 1.3 µs High-Speed Mode, CB = 100pF max(2) 160 ns High-Speed Mode, CB = 400pF max(2) 320 ns HIGH Period of the SCL Clock tHIGH Standard Mode 4.0 µs Fast Mode 600 ns High-Speed Mode, CB = 100pF max(2) 60 ns High-Speed Mode, CB = 400pF max(2) 120 ns Setup Time for a Repeated START tSU;STA Standard Mode 4.7 µs Condition Fast Mode 600 ns High-Speed Mode 160 ns Data Setup Time tSU;DAT Standard Mode 250 ns Fast Mode 100 ns High-Speed Mode 10 ns Data Hold Time tHD;DAT Standard Mode 0 3.45 µs Fast Mode 0 0.9 µs High-Speed Mode, CB = 100pF max(2) 0(3) 70 ns High-Speed Mode, CB = 400pF max(2) 0(3) 150 ns Rise Time of SCL Signal tRCL Standard Mode 1000 ns Fast Mode 20 + 0.1CB 300 ns High-Speed Mode, CB = 100pF max(2) 10 40 ns High-Speed Mode, CB = 400pF max(2) 20 80 ns Rise Time of SCL Signal After a tRCL1 Standard Mode 1000 ns Repeated START Condition and Fast Mode 20 + 0.1CB 300 ns After an Acknowledge Bit High-Speed Mode, CB = 100pF max(2) 10 80 ns High-Speed Mode, CB = 400pF max(2) 20 160 ns Fall Time of SCL Signal tFCL Standard Mode 300 ns Fast Mode 20 + 0.1CB 300 ns High-Speed Mode, CB = 100pF max(2) 10 40 ns High-Speed Mode, CB = 400pF max(2) 20 80 ns TIMING CHARACTERISTICS(1) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. TIMING DIAGRAM t R t BUF t LOW t F t HD; STA t SP t HD; STA t SU; STA t HD; DAT t SU; DAT t HIGH t SU; STO SCL SDA START REPEATED START STOP NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated. (3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. |
Số phần tương tự - ADS7828E |
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Mô tả tương tự - ADS7828E |
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