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ADS7822EB/250 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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ADS7822EB/250 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 28 page www.ti.com DIGITAL INTERFACE Signal Levels Serial Interface CS/SHDN D OUT DCLOCK t DATA t SUCS t CYC t CONV Power Down t SMPL Note:(1)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith CS LOW, theA/DwilloutputLSB-Firstdatathenfollowedwithzeroesindefinitely. B11 (MSB) B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (1) Null Bit Hi-Z Hi-Z B11 B10 B9 B8 Null Bit CS/SHDN D OUT DCLOCK t CONV t DATA t SUCS t CSD t CYC PowerDown t SMPL Note:(1)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith CS LOW, theA/Dwilloutputzeroesindefinitely. t enceinput :Duringthistime,thebiascurrentandthecomparatorpowerdownandtherefer DATA becomesahighimpedancenode,leavingtheCLKrunningtoclockoutLSB-firstdataorzeroes. B11 (MSB) B10 B9 B8 B7 B6 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 Null Bit Hi-Z Hi-Z B5 B6 B7 B8 B9 B10 B11 (1) t CSD ADS7822 SBAS062C – JANUARY 1996 – REVISED AUGUST 2007 The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5V reference, the internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the The digital inputs of the ADS7822 can accommodate output code. When the external reference is 50mV, logic levels up to 6V regardless of the value of VCC. the potential error contribution from the internal noise Thus, the ADS7822 can be powered at 3V and still will be 50 times larger—16 LSBs. The errors due to accept inputs from logic powered at 5V. the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. The CMOS digital output (DOUT) will swing 0V to VCC. If VCC is 3V and this output is connected to a 5V For more information regarding noise, consult the CMOS logic input, then that IC may require more typical characteristic curves Effective Number of Bits supply current than normal and may have a slightly vs Reference Voltage and Peak-to-Peak Noise vs longer propagation delay. Reference Voltage. Note that the effective number of bits (ENOB) figure is calculated based on the converter signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as The ADS7822 communicates with microprocessors follows: and other digital systems via a synchronous 3-wire serial interface, as shown in Figure 22 and Table 1. SINAD = 6.02 • ENOB + 1.76 The DCLOCK signal synchronizes the data transfer With lower reference voltages, extra care should be with each bit being transmitted on the falling edge of taken to provide a clean layout including adequate DCLOCK. Most receiving systems will capture the bypassing, a clean power supply, a low-noise bitstream on the rising edge of DCLOCK. However, if reference, and a low-noise input signal. Because the the minimum hold time for DOUT is acceptable, the LSB size is lower, the converter will also be more system can use the falling edge of DCLOCK to sensitive to external sources of error such as nearby capture each bit. digital signals and electromagnetic interference. Figure 22. Basic Timing Diagrams Copyright © 1996–2007, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS7822 |
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Mô tả tương tự - ADS7822EB/250 |
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