7

®

ADS7821

READING DATA

The ADS7821 outputs full or byte-reading parallel data in

Straight Binary data output format. The parallel output will

be active when R/C (pin 24) is HIGH and CS (pin 25) is

LOW. Any other combination of CS and R/C will tri-state

the parallel output. Valid conversion data can be read in a

full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and

pins 15-22. BYTE (pin 23) can be toggled to read both bytes

within one conversion cycle. Refer to Table III for ideal

output codes and Figure 2 for bit locations relative to the

state of BYTE.

PARALLEL OUTPUT (During a Conversion)

After conversion ‘n’ has been initiated, valid data from

conversion ‘n-1’ can be read and will be valid up to 5

µs after

the start of conversion ‘n’. Do not attempt to read data from

5

µs after the start of conversion ‘n’ until BUSY (pin 26)

goes HIGH; this may result in reading invalid data. Refer to

Table IV and Figures 3 through 5 for timing specifications.

Note! For the best possible performance, data should not be

read during a conversion. The switching noise of the asyn-

chronous data transfer can cause digital feedthrough degrad-

ing the converter’s performance.

The number of control lines can be reduced by tying CS

LOW while using R/C to initiate conversions and activate

the output mode of the converter. See Figure 3.

DIGITAL OUTPUT

STRAIGHT BINARY

DESCRIPTION

ANALOG INPUT

BINARY CODE

HEX CODE

Full Scale Range

0 to +5V

Least Significant

76

µV

Bit (LSB)

Full Scale

4.999924V

1111 1111 1111 1111

FFFF

Midscale

2.5V

1000 0000 0000 0000

8000

One LSB below

2.499924V

0111 1111 1111 1111

7FFF

Midscale

Zero Scale

0V

0000 0000 0000 0000

0000

Table III. Ideal Input Voltages and Output Codes.

PARALLEL OUTPUT (After a Conversion)

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 26) will go HIGH. Valid data

from conversion ‘n’ will be available on D15-D0 (pin 6-13

and 15-22). BUSY going HIGH can be used to latch the

data. Refer to Table IV and Figures 3 through 5 for timing

specifications.

FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).

Bit 0 (LSB)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 15 (MSB)

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

6

7

8

9

10

11

12

13

14

23

22

21

20

19

18

17

16

15

ADS7821

BYTE LOW

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15 (MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

6

7

8

9

10

11

12

13

14

23

22

21

20

19

18

17

16

15

ADS7821

BYTE HIGH

+5V

SYMBOL

DESCRIPTION

MIN

TYP MAX UNITS

Convert Pulse Width

40

5000

ns

Data Valid Delay

8

µs

after Start of Conversion

BUSY Delay

65

ns

from Start of Conversion

BUSY LOW

8

µs

BUSY Delay after

220

ns

End of Conversion

Aperture Delay

40

ns

Conversion Time

7.6

8

µs

Acquisition Time

2

µs

Bus Relinquish Time

10

35

83

ns

BUSY Delay after Data Valid

50

200

ns

Previous Data Valid

5

µs

after Start of Conversion

Throughput Time

9

10

µs

R/C to CS Setup Time

10

ns

Time Between Conversions

10

µs

Bus Access Time

10

83

ns

and BYTE Delay

TABLE IV. Conversion Timing.